FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/clk_edge.v @ 52:cbfcc480d61b

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fpga build: migrate to yosys-tee wrapper
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 03 Oct 2023 18:17:58 +0000
parents 0f74428c177c
children
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
7db5fd6646df fpga/sniffer-basic: initial version
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2 * This Verilog module captures the logic that detects rising edges of SIM_CLK
7db5fd6646df fpga/sniffer-basic: initial version
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3 * for the purpose of counting them.
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4 */
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7db5fd6646df fpga/sniffer-basic: initial version
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6 module clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
7db5fd6646df fpga/sniffer-basic: initial version
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7db5fd6646df fpga/sniffer-basic: initial version
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8 input IntClk;
7db5fd6646df fpga/sniffer-basic: initial version
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9 input SIM_CLK_sync;
7db5fd6646df fpga/sniffer-basic: initial version
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10 output SIM_CLK_edge;
7db5fd6646df fpga/sniffer-basic: initial version
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7db5fd6646df fpga/sniffer-basic: initial version
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12 reg prev_state;
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7db5fd6646df fpga/sniffer-basic: initial version
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14 always @(posedge IntClk)
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15 prev_state <= SIM_CLK_sync;
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7db5fd6646df fpga/sniffer-basic: initial version
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17 assign SIM_CLK_edge = SIM_CLK_sync && !prev_state;
7db5fd6646df fpga/sniffer-basic: initial version
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18
7db5fd6646df fpga/sniffer-basic: initial version
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19 endmodule