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doc/Sniffing-hw-setup: mv-sniffer is here
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Oct 2023 05:55:09 +0000
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1 module board ();
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2
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3 wire GND;
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4 wire SIM_VCC, SIM_RST, SIM_CLK, SIM_IO;
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5 wire FPGA_VCC, FPGA_RST, FPGA_CLK, FPGA_IO;
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6
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7 /* headers connecting to other boards */
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8
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9 header_6pin hdr_sim (.pin_1(SIM_VCC),
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10 .pin_2(SIM_RST),
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11 .pin_3(SIM_CLK),
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12 .pin_4(SIM_IO),
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13 .pin_5(GND),
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14 .pin_6(GND)
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15 );
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16
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17 header_6pin hdr_fpga (.pin_1(FPGA_VCC),
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18 .pin_2(GND),
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19 .pin_3(FPGA_RST),
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20 .pin_4(FPGA_CLK),
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21 .pin_5(FPGA_IO),
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22 .pin_6() /* unused */
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23 );
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24
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25 /* sniffing buffer IC */
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26
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27 ic_74LVC4T3144 buffer ( .GND(GND),
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28 .VccA(SIM_VCC),
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29 .VccB(FPGA_VCC),
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30 .nOE(GND),
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31 .A1(SIM_RST),
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32 .A2(SIM_CLK),
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33 .A3(SIM_IO),
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34 .YA4(), /* no connect */
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35 .YB1(FPGA_RST),
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36 .YB2(FPGA_CLK),
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37 .YB3(FPGA_IO),
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38 .B4(GND)
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39 );
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40
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41 /* bypass caps next to buffer IC supply pins */
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42
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43 capacitor C1 (SIM_VCC, GND);
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44 capacitor C2 (FPGA_VCC, GND);
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45
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46 /* pull-down resistors on buffer IC outputs, for PPD mode */
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47
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48 resistor R1 (FPGA_RST, GND);
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49 resistor R2 (FPGA_CLK, GND);
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50 resistor R3 (FPGA_IO, GND);
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51
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52 endmodule