FreeCalypso > hg > fc-sim-sniff
annotate fpga/common/icestick.pcf @ 58:95ed46b5f8f1 default tip
doc/Sniffing-hw-setup: mv-sniffer is here
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 04 Oct 2023 05:55:09 +0000 |
parents | 990ecafdddb4 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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1 # Pin Constraint File for the HK1X FPGA as wired on the Icestick board, |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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2 # adapted for SIMtrace-ice application. |
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Mychaela Falconia <falcon@freecalypso.org>
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3 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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4 # Board essentials |
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Mychaela Falconia <falcon@freecalypso.org>
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5 set_io CLK12 21 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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6 set_io LED1 99 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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7 set_io LED2 98 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 set_io LED3 97 |
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Mychaela Falconia <falcon@freecalypso.org>
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9 set_io LED4 96 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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10 set_io LED5 95 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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11 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 # FT2232H UART channel, signal names are from FT2232H DTE perspective, |
7db5fd6646df
fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 # the logic in the FPGA has to act as DCE. |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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15 set_io UART_TxD 9 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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16 set_io UART_RxD 8 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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17 set_io UART_RTS 7 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 set_io UART_CTS 4 |
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Mychaela Falconia <falcon@freecalypso.org>
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19 set_io UART_DTR 3 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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20 set_io UART_DSR 2 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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21 set_io UART_DCD 1 |
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fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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22 |
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Mychaela Falconia <falcon@freecalypso.org>
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23 # SIM sniffing interface, receiving outputs from the level shifter board |
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fpga/sniffer-basic: drive pin 115 high for cardem pod
Mychaela Falconia <falcon@freecalypso.org>
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24 # via J1 header pins, plus output line for OD buffer in cardem application. |
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Mychaela Falconia <falcon@freecalypso.org>
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25 |
26
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fpga/sniffer-basic: drive pin 115 high for cardem pod
Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 set_io SIM_RST_in 112 |
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fpga/sniffer-basic: drive pin 115 high for cardem pod
Mychaela Falconia <falcon@freecalypso.org>
parents:
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27 set_io SIM_CLK_in 113 |
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fpga/sniffer-basic: drive pin 115 high for cardem pod
Mychaela Falconia <falcon@freecalypso.org>
parents:
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28 set_io SIM_IO_in 114 |
e5c5162b3a8c
fpga/sniffer-basic: drive pin 115 high for cardem pod
Mychaela Falconia <falcon@freecalypso.org>
parents:
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29 set_io SIM_IO_out 115 |