FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/sync_inputs.v @ 58:95ed46b5f8f1 default tip

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
doc/Sniffing-hw-setup: mv-sniffer is here
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Oct 2023 05:55:09 +0000
parents 0f74428c177c
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This Verilog module captures the input synchronizer logic: passing all 3
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 * SIM sniffer inputs through double-DFF synchronizers to bring them into
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 * our internal clock domain.
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 */
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 module sync_inputs (IntClk, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 SIM_IO_in, SIM_IO_sync);
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 input IntClk;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 output SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 reg SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 reg SIM_RST_sync1, SIM_CLK_sync1, SIM_IO_sync1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 SIM_RST_sync1 <= SIM_RST_in;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 SIM_RST_sync <= SIM_RST_sync1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 SIM_CLK_sync1 <= SIM_CLK_in;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 SIM_CLK_sync <= SIM_CLK_sync1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 SIM_IO_sync1 <= SIM_IO_in;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 SIM_IO_sync <= SIM_IO_sync1;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 endmodule