FreeCalypso > hg > fc-sim-sniff

comparison fpga/sniffer-pps/reset_detect.v @ 28:0f74428c177c

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
fpga/sniffer-pps: first version
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:05:23 +0000
parents fpga/sniffer-basic/reset_detect.v@7db5fd6646df
children
comparison
equal deleted inserted replaced
27:990ecafdddb4 28:0f74428c177c
1 /*
2 * This Verilog module captures the logic that detects SIM_RST transitions
3 * in either direction.
4 */
5
6 module reset_detect (IntClk, SIM_RST_sync, SIM_RST_toggle);
7
8 input IntClk;
9 input SIM_RST_sync;
10 output SIM_RST_toggle;
11
12 reg prev_state;
13
14 always @(posedge IntClk)
15 prev_state <= SIM_RST_sync;
16
17 assign SIM_RST_toggle = SIM_RST_sync != prev_state;
18
19 endmodule