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comparison fpga/sniffer-pps/sniff_rx.v @ 28:0f74428c177c

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fpga/sniffer-pps: first version
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:05:23 +0000
parents fpga/sniffer-basic/sniff_rx.v@db8acc067542
children ab37fcb71744
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27:990ecafdddb4 28:0f74428c177c
1 /*
2 * This Verilog module captures the ISO 7816-3 character sniffing receiver.
3 */
4
5 module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
6 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
7
8 input IntClk;
9 input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
10 output Rx_strobe, Rx_error;
11 output [7:0] Rx_char;
12 output Rx_start_bit, Rx_parity_bit;
13
14 wire SIM_CLK_edge;
15
16 clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
17
18 wire [9:0] etu_0p5, etu_1p0, etu_1p5;
19
20 /* Fi/Di=372 only for now */
21 assign etu_0p5 = 10'd185;
22 assign etu_1p0 = 10'd371;
23 assign etu_1p5 = 10'd557;
24
25 reg rx_active;
26 reg [9:0] clk_count;
27 reg [3:0] bit_count;
28 reg [9:0] shift_reg;
29
30 always @(posedge IntClk)
31 if (!SIM_RST_sync)
32 rx_active <= 1'b0;
33 else if (!rx_active && !SIM_IO_sync)
34 begin
35 rx_active <= 1'b1;
36 clk_count <= etu_0p5;
37 bit_count <= 4'd0;
38 end
39 else if (rx_active && SIM_CLK_edge)
40 begin
41 if (clk_count != 10'd0)
42 clk_count <= clk_count - 10'd1;
43 else begin
44 shift_reg <= {SIM_IO_sync,shift_reg[9:1]};
45 bit_count <= bit_count + 4'd1;
46 if (bit_count == 4'd9)
47 clk_count <= etu_1p5;
48 else
49 clk_count <= etu_1p0;
50 if (bit_count == 4'd10)
51 rx_active <= 1'b0;
52 end
53 end
54
55 assign Rx_strobe = rx_active && SIM_CLK_edge && clk_count == 10'd0 &&
56 bit_count == 4'd10;
57 assign Rx_error = Rx_strobe && !SIM_IO_sync;
58 assign Rx_char = shift_reg[8:1];
59 assign Rx_start_bit = shift_reg[0];
60 assign Rx_parity_bit = shift_reg[9];
61
62 endmodule