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comparison fpga/sniffer-pps/top.v @ 28:0f74428c177c

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fpga/sniffer-pps: first version
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:05:23 +0000
parents fpga/sniffer-basic/top.v@e5c5162b3a8c
children dc99c9962aed
comparison
equal deleted inserted replaced
27:990ecafdddb4 28:0f74428c177c
1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST_in, SIM_CLK_in,
3 SIM_IO_in, SIM_IO_out);
4
5 input CLK12;
6 output LED1, LED2, LED3, LED4, LED5;
7
8 input UART_TxD, UART_RTS, UART_DTR;
9 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
10
11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
12 output SIM_IO_out;
13
14 /* input synchronizers */
15
16 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
17
18 sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
19 SIM_IO_in, SIM_IO_sync);
20
21 /* character receiver */
22
23 wire Rx_strobe, Rx_error;
24 wire [7:0] Rx_char;
25 wire Rx_start_bit, Rx_parity_bit;
26
27 sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
28 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
29
30 /* PPS catcher */
31
32 wire pos_PPS_resp_PPS1, pos_PPS_resp_PCK;
33
34 pps_catcher pps (CLK12, SIM_RST_sync, Rx_strobe, Rx_char,
35 pos_PPS_resp_PPS1, pos_PPS_resp_PCK);
36
37 /* explicit detection of RST transitions */
38
39 wire SIM_RST_toggle;
40
41 reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);
42
43 /* output to the host */
44
45 wire Tx_trigger;
46 wire [15:0] Tx_data;
47
48 assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
49 assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,1'b0,
50 pos_PPS_resp_PCK,pos_PPS_resp_PPS1,
51 Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};
52
53 uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);
54
55 /* UART modem control outputs: unused */
56
57 assign UART_CTS = 1'b1;
58 assign UART_DSR = 1'b0;
59 assign UART_DCD = 1'b0;
60
61 /* board LEDs */
62
63 assign LED1 = 1'b1;
64 assign LED2 = 1'b0;
65 assign LED3 = 1'b1;
66 assign LED4 = 1'b0;
67 assign LED5 = SIM_RST;
68
69 /* SIM_IO_out dummy: if someone mistakenly connects an Icestick board with
70 * this FPGA image in it to a cardem pod instead of the sniffing one,
71 * we ensure that the 74LVC1G07 OD buffer remains off by feeding logic HIGH
72 * to this buffer.
73 */
74
75 assign SIM_IO_out = 1'b1;
76
77 endmodule