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comparison doc/PPS-catcher-FSM @ 48:1068f9fd41d5

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doc: project rename
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 21 Sep 2023 06:31:34 +0000
parents c2fc75655937
children
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47:7c9bf72d460f 48:1068f9fd41d5
1 This document describes the PPS catcher state machine that has been implemented 1 This document describes the PPS catcher state machine that has been implemented
2 in the SIMtrace3 sniffer FPGA, using a sort of verbal pseudocode. 2 in the FPGA part of FreeCalypso SIMsniff, using a sort of verbal pseudocode.
3 3
4 INITIAL: 4 INITIAL:
5 5
6 This state will be entered upon reset (held in this state while RST is low). 6 This state will be entered upon reset (held in this state while RST is low).
7 Must receive 8'h3B to proceed to state T0, otherwise transition to DONE. 7 Must receive 8'h3B to proceed to state T0, otherwise transition to DONE.