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comparison fpga/tools/yosys-wrap @ 18:af1a9732da1f

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FPGA build: include yosys-wrap in this repository
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 19:25:35 +0000
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17:41e6026e5d1a 18:af1a9732da1f
1 #!/bin/sh
2
3 if [ $# -lt 3 ]
4 then
5 echo "usage: $0 top-module json-output verilog-src..." 1>&2
6 exit 1
7 fi
8
9 top="$1"
10 json="$2"
11
12 shift
13 shift
14
15 rm -f "$json"
16 yosys -p "synth_ice40 -top $top -json $json" "$@"
17
18 if [ -f "$json" ]
19 then
20 echo "$json created, declaring success"
21 exit 0
22 else
23 echo "$json NOT created, declaring error"
24 exit 1
25 fi