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doc/Sniffer-FPGA-design: update for working status
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 06:37:58 +0000
parents 41e6026e5d1a
children 695ca51e1564
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24:f1e7795557b1 25:c03a882cc49e
1 The first FPGA logic function in the SIMtrace-ice project has been implemented 1 The first version of SIMtrace3 sniffer FPGA (the version in fpga/sniffer-basic,
2 and is now waiting to be tested: it is the basic sniffer FPGA in the 2 no PPS catcher, F/D=372 only for now) has been implemented, tested and proven
3 fpga/sniffer-basic directory. It is an FPGA image for Lattice Icestick, an 3 working. It is an FPGA image for Lattice Icestick, an inexpensive off-the-shelf
4 inexpensive off-the-shelf iCE40 FPGA board, and it implements the function of 4 iCE40 FPGA board, and it implements the function of passive sniffing: receiving
5 passive sniffing: receiving level-shifted SIM RST, CLK and I/O signals from the 5 level-shifted SIM RST, CLK and I/O signals from the 74LVC4T3144 buffer and
6 74LVC4T3144 buffer and capturing all exchanges that happen on the SIM interface 6 capturing all exchanges that happen on the SIM interface between a GSM ME or
7 between a GSM ME or other interface device (ME/ID for short) and a SIM. 7 other interface device (ME/ID for short) and a SIM.
8 8
9 This FPGA gateware function is currently waiting to be tested: some custom 9 Hardware architecture and FPGA design principle
10 hardware needs to be assembled before the FPGA can be tested. The PCB fab order 10 ===============================================
11 for our mv-sniffer adapter board has just been placed; we will need to receive
12 the PCB, get it populated, and also populate the missing pin headers on the
13 Icestick board before we can test our FPGA.
14 11
15 The two principal components of the Icestick board are an iCE40HX1K FPGA and an 12 The two principal components of the Icestick board are an iCE40HX1K FPGA and an
16 FT2232H-based USB host interface. Our sniffer logic function in the FPGA 13 FT2232H-based USB host interface. Our sniffer logic function in the FPGA
17 operates principally as a byte forwarder from the ISO 7816-3 sniffer block to 14 operates principally as a byte forwarder from the ISO 7816-3 sniffer block to
18 the FT2232H UART: every time the bus sniffer block captures a character (in ISO 15 the FT2232H UART: every time the bus sniffer block captures a character (in ISO