comparison fpga/sniffer-basic/top.v @ 26:e5c5162b3a8c

fpga/sniffer-basic: drive pin 115 high for cardem pod
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 18:05:09 +0000
parents 3da4676dafa8
children dc99c9962aed
comparison
equal deleted inserted replaced
25:c03a882cc49e 26:e5c5162b3a8c
1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS, 1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST, SIM_CLK, SIM_IO); 2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST_in, SIM_CLK_in,
3 SIM_IO_in, SIM_IO_out);
3 4
4 input CLK12; 5 input CLK12;
5 output LED1, LED2, LED3, LED4, LED5; 6 output LED1, LED2, LED3, LED4, LED5;
6 7
7 input UART_TxD, UART_RTS, UART_DTR; 8 input UART_TxD, UART_RTS, UART_DTR;
8 output UART_RxD, UART_CTS, UART_DSR, UART_DCD; 9 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
9 10
10 input SIM_RST, SIM_CLK, SIM_IO; 11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
12 output SIM_IO_out;
11 13
12 /* input synchronizers */ 14 /* input synchronizers */
13 15
14 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync; 16 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
15 17
16 sync_inputs sync (CLK12, SIM_RST, SIM_RST_sync, SIM_CLK, SIM_CLK_sync, 18 sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
17 SIM_IO, SIM_IO_sync); 19 SIM_IO_in, SIM_IO_sync);
18 20
19 /* character receiver */ 21 /* character receiver */
20 22
21 wire Rx_strobe, Rx_error; 23 wire Rx_strobe, Rx_error;
22 wire [7:0] Rx_char; 24 wire [7:0] Rx_char;
54 assign LED2 = 1'b0; 56 assign LED2 = 1'b0;
55 assign LED3 = 1'b1; 57 assign LED3 = 1'b1;
56 assign LED4 = 1'b0; 58 assign LED4 = 1'b0;
57 assign LED5 = SIM_RST; 59 assign LED5 = SIM_RST;
58 60
61 /* SIM_IO_out dummy: if someone mistakenly connects an Icestick board with
62 * this FPGA image in it to a cardem pod instead of the sniffing one,
63 * we ensure that the 74LVC1G07 OD buffer remains off by feeding logic HIGH
64 * to this buffer.
65 */
66
67 assign SIM_IO_out = 1'b1;
68
59 endmodule 69 endmodule