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comparison doc/Sniffing-hw-setup @ 36:f1c3dd2173d3

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doc/Sniffing-hw-setup: document written
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 30 Aug 2023 02:22:44 +0000
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children 1068f9fd41d5
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35:695ca51e1564 36:f1c3dd2173d3
1 The hardware setup for SIM sniffing with SIMtrace3 consists of the following
2 components:
3
4 * The same SIMtrace FPC cables (going from a SIM socket to the 6-pin FPC
5 connector) that were originally developed for SIMtrace1/2 and are sold by
6 Sysmocom;
7
8 * An off-the-shelf Lattice Icestick FPGA board (sold by Digi-Key, for example)
9 that has been outfitted with header pins: the board ships with empty PTHs
10 (plated through holes) at J1, hence a small soldering job is required to
11 populate this header;
12
13 * Some in-between components described below.
14
15 For the in-between components of the last bullet point above, there are 3
16 possibilities, each described in its own section below.
17
18 HW setup version 0
19 ==================
20
21 (works today)
22
23 The piece between the SIMtrace FPC cable from Sysmocom and the Icestick FPGA
24 board is the "SIMtrace FPC passive connection" adapter (design files in
25 boards/sim-fpc-pasv directory) from the fall of 2022. The electrical connection
26 from the ME/ID SIM socket to the physical SIM is direct and physically
27 continuous (no switches, no Heisenbugs), and a trio of FPGA I/O pins (configured
28 as inputs) are connected directly to this SIM bus with jumper wires.
29
30 This hw setup is intended only as a very temporary prototype until we get hw
31 setup version 1 described below. The present hw setup version 0 works ONLY if
32 the ME/ID operates with class B voltage levels: if you try class A (5V), you'll
33 instantly damage the FPGA by grossly exceeding its Absolute Maximum Ratings
34 (don't do it!), and if you try class C (1.8V), the high level will fall right
35 between Vil_max and Vih_min, causing the FPGA to receive garbage. However, this
36 otherwise-unusable hw setup was good enough to prove the FPGA logic working,
37 using an FCDEV3B as the ME/ID, manually forced into class B operation.
38
39 HW setup version 1
40 ==================
41
42 (coming very soon)
43
44 Compared to hw setup version 0, one extra component is added between the
45 sim-fpc-pasv adapter and the Icestick board: another little adapter board called
46 "SIMtrace-ice multivolt sniffer", design files in boards/mv-sniffer directory.
47 The only active component on the mv-sniffer board is a Nexperia 74LVC4T3144 dual
48 supply logic voltage level translator IC, powered from SIM_VCC on its A side
49 and from Icestick board +3.3V rail on its B side.
50
51 The mv-sniffer PCB is currently on its way to FreeCalypso HQ from the PCB fab
52 in China, and once the PCB arrives, assembly will require another trip to
53 Technotronix. Once we have this board assembled, we should have a working
54 SIMtrace3 sniffing path that is fully compatible with all 3 voltage classes,
55 per the original intent of SIMtrace3 project.
56
57 HW setup version 2
58 ==================
59
60 (a little more distant, but will be needed before wider spread)
61
62 The solution with separate sim-fpc-pasv and mv-sniffer boards is expected to be
63 quite inconvenient because of the number of pieces required - clutter on the lab
64 bench - plus poor electrical design with jumper wires between the two boards
65 extending the electrical length of the SIM bus before the LVC buffer. In the
66 fully polished version of SIMtrace3, these two adapter boards will need to be
67 combined into one. The final SIMtrace3 sniffer pod is expected to be a single
68 board (still very simple and low cost) featuring the following components:
69
70 1) SIMtrace FPC connector
71 2) SIM socket
72 3) 74LVC4T3144 buffer IC
73 4) SIM bus solidly connected between components 1, 2 and 3
74 5) A header for FPGA board connection, wired to the 'B' side of component 3