--- a/doc/Sniffer-FPGA-design	Thu Sep 21 05:00:50 2023 +0000
+++ b/doc/Sniffer-FPGA-design	Thu Sep 21 06:31:34 2023 +0000
@@ -1,11 +1,11 @@
-FPGA component of SIMtrace3 sniffer
-===================================
+FPGA component of FreeCalypso SIMsniff
+======================================
 
-The SIM interface sniffing apparatus of SIMtrace3 consists of a sniffer pod
-(hardware adapter with level shifters) and a Lattice Icestick FPGA board, loaded
-with the appropriate gateware image from the present project.  This document
-describes the design and operation of the FPGA component of this SIMtrace3
-sniffing solution.
+The present FreeCalypso solution for SIM interface sniffing consists of a
+sniffer pod (hardware adapter with level shifters) and a Lattice Icestick FPGA
+board, loaded with the appropriate gateware image from the present project.
+This document describes the design and operation of the FPGA component of
+FC SIMsniff.
 
 Hardware architecture and FPGA design principle
 ===============================================
@@ -178,11 +178,12 @@
 Only the card and not the interface device (ISO 7816-3 terminology) determines
 which coding convention is used, direct or inverse.  So far we (FreeCalypso)
 have not yet encountered a real-life SIM that uses the inverse convention, only
-the direct convention kind.  In the sniffer function of SIMtrace-ice, we are
-going to keep our FPGA gateware simple in this regard and punt all inverse
-convention handling to the software application on the host computer: the FPGA
-passes the 9 received bits (8 data bits and 1 parity bit) to the 16-bit UART
-message as-is, without inverting or reordering them.
+the direct convention kind.  The approach taken in FC SIMsniff is that the FPGA
+is mostly (except for the integrated PPS catcher) oblivious to the coding
+convention: it passes the 9 received bits (8 data bits and 1 parity bit) to the
+16-bit UART message as-is, without inverting or reordering them.  The coding
+convention and the parity check are then handled in simsniff-dec host
+application.
 
 Integrated PPS catcher
 ======================
@@ -229,7 +230,7 @@
 receiver block, such as original Osmocom SIMtrace in which the local CPU core
 and the ISO 7816-3 receiver sit in the same AT91SAMx chip, don't suffer from
 this problem: with a local (dedicated, embedded) CPU so close, the firmware can
-react and intervene in time.  However, in the case of our SIMtrace3, the nearest
+react and intervene in time.  However, in the case of FC SIMsniff, the nearest
 CPU is the host computer separated by UART and USB links - not closely coupled
 enough to provide the degree of real-time response that is needed here.  Someone
 could say that we should stick a soft CPU core with firmware into our FPGA - but