--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/sniffer-basic/top.v	Mon Aug 21 00:52:00 2023 +0000
@@ -0,0 +1,59 @@
+module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
+	    UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST, SIM_CLK, SIM_IO);
+
+input CLK12;
+output LED1, LED2, LED3, LED4, LED5;
+
+input UART_TxD, UART_RTS, UART_DTR;
+output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
+
+input SIM_RST, SIM_CLK, SIM_IO;
+
+/* input synchronizers */
+
+wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
+
+sync_inputs sync (CLK12, SIM_RST, SIM_RST_sync, SIM_CLK, SIM_CLK_sync,
+		  SIM_IO, SIM_IO_sync);
+
+/* character receiver */
+
+wire Rx_strobe, Rx_error;
+wire [7:0] Rx_char;
+wire Rx_start_bit, Rx_parity_bit;
+
+sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
+		   Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
+
+/* explicit detection of RST transitions */
+
+wire SIM_RST_toggle;
+
+reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);
+
+/* output to the host */
+
+wire Tx_trigger;
+wire [15:0] Tx_data;
+
+assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
+assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,3'b000,
+		  Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};
+
+uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);
+
+/* UART modem control outputs: unused */
+
+assign UART_CTS = 1'b1;
+assign UART_DSR = 1'b0;
+assign UART_DCD = 1'b0;
+
+/* board LEDs */
+
+assign LED1 = 1'b1;
+assign LED2 = 1'b0;
+assign LED3 = 1'b1;
+assign LED4 = 1'b0;
+assign LED5 = !SIM_RST;
+
+endmodule