--- a/doc/Sniffing-hw-setup	Wed Oct 04 03:54:00 2023 +0000
+++ b/doc/Sniffing-hw-setup	Wed Oct 04 05:55:09 2023 +0000
@@ -15,50 +15,36 @@
 For the in-between components of the last bullet point above, there are 3
 possibilities, each described in its own section below.
 
-HW setup version 0
+HW setup version 1
 ==================
 
 (works today)
 
-The piece between the SIMtrace FPC cable from Sysmocom and the Icestick FPGA
-board is the "SIMtrace FPC passive connection" adapter (design files in
-boards/sim-fpc-pasv directory) from the fall of 2022.  The electrical connection
-from the ME/ID SIM socket to the physical SIM is direct and physically
-continuous (no switches, no Heisenbugs), and a trio of FPGA I/O pins (configured
-as inputs) are connected directly to this SIM bus with jumper wires.
+In this solution there are two little ad hoc boards sitting between the SIMtrace
+FPC cable and the Icestick board:
 
-This hw setup is intended only as a very temporary prototype until we get hw
-setup version 1 described below.  The present hw setup version 0 works ONLY if
-the ME/ID operates with class B voltage levels: if you try class A (5V), you'll
-instantly damage the FPGA by grossly exceeding its Absolute Maximum Ratings
-(don't do it!), and if you try class C (1.8V), the high level will fall right
-between Vil_max and Vih_min, causing the FPGA to receive garbage.  However, this
-otherwise-unusable hw setup was good enough to prove the FPGA logic working,
-using an FCDEV3B as the ME/ID, manually forced into class B operation.
+* sim-fpc-pasv board produced in the fall of 2022
+* mv-sniffer board produced in the fall of 2023
 
-HW setup version 1
-==================
-
-(coming very soon)
+The first board (sim-fpc-pasv) passively interconnects an FPC connector for
+SIMtrace cables, a physical SIM socket and a bunch of 2.54 mm header pins,
+bringing out all lines of the SIM-ME electrical interface.  This board was
+originally produced a year ago for the purpose of observing SIM voltages and
+clocks with an oscilloscope.  The second board adds one active component:
+Nexperia 74LVC4T3144 dual supply logic voltage level translator IC, powered
+from SIM_VCC on its A side and from Icestick board +3.3V rail on its B side.
 
-Compared to hw setup version 0, one extra component is added between the
-sim-fpc-pasv adapter and the Icestick board: another little adapter board called
-"SIMtrace-ice multivolt sniffer", design files in boards/mv-sniffer directory.
-The only active component on the mv-sniffer board is a Nexperia 74LVC4T3144 dual
-supply logic voltage level translator IC, powered from SIM_VCC on its A side
-and from Icestick board +3.3V rail on its B side.
-
-The mv-sniffer PCB has been fabricated and received at FreeCalypso HQ, but we
-still need to get it assembled, which will require at least one trip to
-Technotronix, or maybe even two trips.  Once we have this board assembled, we
-should have a working SIM sniffing path that is fully compatible with all 3
-voltage classes, per the original intent of FC SIMsniff project.
+The buffer IC receives (sniffs) the SIM-ME electrical interface at whichever
+voltage the ME puts out (everything from 1.8V to 5V is accepted) and puts out
+the same signals at the fixed logic voltage level needed by the FPGA on the
+Icestick; the FPGA then sniffs the ISO 7816-3 protocol just above the electrical
+level.
 
 Wire assignments for this HW setup
 ----------------------------------
 
 A 6-wire ribbon cable, cut from a standard multicolor ribbon cable spool and
-outfitted with custom crimped connectors, will be used to make the connection
+outfitted with custom crimped connectors, is used to make the connection
 between sim-fpc-pasv and mv-sniffer boards.  Wire color assignments in this
 ad hoc connection cable are:
 
@@ -76,8 +62,8 @@
 
 (a little more distant, but will be needed before wider spread)
 
-The solution with separate sim-fpc-pasv and mv-sniffer boards is expected to be
-quite inconvenient because of the number of pieces required - clutter on the lab
+The solution with separate sim-fpc-pasv and mv-sniffer boards is quite
+inconvenient because of the number of pieces required - clutter on the lab
 bench - plus poor electrical design with jumper wires between the two boards
 extending the electrical length of the SIM bus before the LVC buffer.  In the
 fully polished version of FC SIMsniff, these two adapter boards will need to be
@@ -90,3 +76,20 @@
 3) 74LVC4T3144 buffer IC
 4) SIM bus solidly connected between components 1, 2 and 3
 5) A header for FPGA board connection, wired to the 'B' side of component 3
+
+HW setup version 0 (historical)
+===============================
+
+In the beginning of FC SIMsniff project, there was no new custom hardware - but
+we did have our sim-fpc-pasv board from a year ago, and we got the Icestick
+board outfitted with header pins.  Our first hw setup thus consisted of jumper
+wires connecting from FPGA I/O pins (plus Icestick GND) directly to SIM bus pins
+on the sim-fpc-pasv adapter.
+
+This hw setup could not be used for any real SIM-ME sniffing: a class A (5V) ME
+would destroy the FPGA (grossly exceeds Absolute Maximum Ratings), while class C
+(1.8V) operation produced by all newer ME (from Calypso+Iota onward) cannot be
+picked up directly by the FPGA as the high logic level falls right between
+Vil_max and Vih_min, causing the FPGA to receive garbage.  However, this setup
+worked with FCDEV3B forced into class B operation, and was used to develop our
+FPGA logic and prove it working before the arrival of mv-sniffer board.