FreeCalypso > hg > fc-sim-sniff
view fpga/sniffer-basic/reset_detect.v @ 48:1068f9fd41d5
doc: project rename
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 21 Sep 2023 06:31:34 +0000 |
parents | 7db5fd6646df |
children |
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/* * This Verilog module captures the logic that detects SIM_RST transitions * in either direction. */ module reset_detect (IntClk, SIM_RST_sync, SIM_RST_toggle); input IntClk; input SIM_RST_sync; output SIM_RST_toggle; reg prev_state; always @(posedge IntClk) prev_state <= SIM_RST_sync; assign SIM_RST_toggle = SIM_RST_sync != prev_state; endmodule