FreeCalypso > hg > fc-sim-sniff
view fpga/sniffer-basic/sniff_rx.v @ 48:1068f9fd41d5
doc: project rename
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 21 Sep 2023 06:31:34 +0000 |
parents | db8acc067542 |
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/* * This Verilog module captures the ISO 7816-3 character sniffing receiver. */ module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync, Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit); input IntClk; input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync; output Rx_strobe, Rx_error; output [7:0] Rx_char; output Rx_start_bit, Rx_parity_bit; wire SIM_CLK_edge; clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge); wire [9:0] etu_0p5, etu_1p0, etu_1p5; /* Fi/Di=372 only for now */ assign etu_0p5 = 10'd185; assign etu_1p0 = 10'd371; assign etu_1p5 = 10'd557; reg rx_active; reg [9:0] clk_count; reg [3:0] bit_count; reg [9:0] shift_reg; always @(posedge IntClk) if (!SIM_RST_sync) rx_active <= 1'b0; else if (!rx_active && !SIM_IO_sync) begin rx_active <= 1'b1; clk_count <= etu_0p5; bit_count <= 4'd0; end else if (rx_active && SIM_CLK_edge) begin if (clk_count != 10'd0) clk_count <= clk_count - 10'd1; else begin shift_reg <= {SIM_IO_sync,shift_reg[9:1]}; bit_count <= bit_count + 4'd1; if (bit_count == 4'd9) clk_count <= etu_1p5; else clk_count <= etu_1p0; if (bit_count == 4'd10) rx_active <= 1'b0; end end assign Rx_strobe = rx_active && SIM_CLK_edge && clk_count == 10'd0 && bit_count == 4'd10; assign Rx_error = Rx_strobe && !SIM_IO_sync; assign Rx_char = shift_reg[8:1]; assign Rx_start_bit = shift_reg[0]; assign Rx_parity_bit = shift_reg[9]; endmodule