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FPGA Makefile: capture yosys stdout
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 01:00:16 +0000
parents 0c321f1ce085
children
line wrap: on
line source

BOMS=	tallied-bom.txt tallied-bom.csv comptab.txt
NETS=	sverp.unet bound.unet pcb-netlist.txt

all:	${BOMS} ${NETS} elements.pcb

sverp.unet:	schem.v ic_74LVC4T3144.v primitives
	ueda-sverp -o $@ schem.v ic_74LVC4T3144.v

bound.unet:	MCL sverp.unet
	unet-bind -c sverp.unet $@

pcb-netlist.txt:	bound.unet
	unet2pcb bound.unet $@

tallied-bom.txt:	MCL
	ueda-mkbom -cr > $@

tallied-bom.csv:	MCL
	ueda-csvbom > $@

comptab.txt:	MCL
	ueda-shortbom > $@

elements.pcb:	MCL
	ueda-getfps -ch | ueda-runm4 > $@

clean:
	rm -f *.unet *.txt *.csv errs elements.pcb