/*
 * This Verilog module captures the input synchronizer logic: passing all 3
 * SIM sniffer inputs through double-DFF synchronizers to bring them into
 * our internal clock domain.
 */

module sync_inputs (IntClk, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
		    SIM_IO_in, SIM_IO_sync);

input IntClk;
input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
output SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
reg SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;

reg SIM_RST_sync1, SIM_CLK_sync1, SIM_IO_sync1;

always @(posedge IntClk)
	SIM_RST_sync1 <= SIM_RST_in;

always @(posedge IntClk)
	SIM_RST_sync <= SIM_RST_sync1;

always @(posedge IntClk)
	SIM_CLK_sync1 <= SIM_CLK_in;

always @(posedge IntClk)
	SIM_CLK_sync <= SIM_CLK_sync1;

always @(posedge IntClk)
	SIM_IO_sync1 <= SIM_IO_in;

always @(posedge IntClk)
	SIM_IO_sync <= SIM_IO_sync1;

endmodule