FreeCalypso > hg > fc-sim-sniff
view fpga/tools/yosys-wrap @ 46:43f678895a3a
simtrace3-sniff-rx: add some annotations to output
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 31 Aug 2023 10:01:40 +0000 |
parents | af1a9732da1f |
children |
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#!/bin/sh if [ $# -lt 3 ] then echo "usage: $0 top-module json-output verilog-src..." 1>&2 exit 1 fi top="$1" json="$2" shift shift rm -f "$json" yosys -p "synth_ice40 -top $top -json $json" "$@" if [ -f "$json" ] then echo "$json created, declaring success" exit 0 else echo "$json NOT created, declaring error" exit 1 fi