module board ();

wire GND;
wire SIM_VCC, SIM_RST, SIM_CLK, SIM_IO;
wire FPGA_VCC, FPGA_RST, FPGA_CLK, FPGA_IO;

/* headers connecting to other boards */

header_6pin hdr_sim (.pin_1(SIM_VCC),
		     .pin_2(SIM_RST),
		     .pin_3(SIM_CLK),
		     .pin_4(SIM_IO),
		     .pin_5(GND),
		     .pin_6(GND)
	);

header_6pin hdr_fpga (.pin_1(FPGA_VCC),
		      .pin_2(GND),
		      .pin_3(FPGA_RST),
		      .pin_4(FPGA_CLK),
		      .pin_5(FPGA_IO),
		      .pin_6()		/* unused */
	);

/* sniffing buffer IC */

ic_74LVC4T3144 buffer ( .GND(GND),
			.VccA(SIM_VCC),
			.VccB(FPGA_VCC),
			.nOE(GND),
			.A1(SIM_RST),
			.A2(SIM_CLK),
			.A3(SIM_IO),
			.YA4(),		/* no connect */
			.YB1(FPGA_RST),
			.YB2(FPGA_CLK),
			.YB3(FPGA_IO),
			.B4(GND)
	);

/* bypass caps next to buffer IC supply pins */

capacitor C1 (SIM_VCC, GND);
capacitor C2 (FPGA_VCC, GND);

/* pull-down resistors on buffer IC outputs, for PPD mode */

resistor R1 (FPGA_RST, GND);
resistor R2 (FPGA_CLK, GND);
resistor R3 (FPGA_IO, GND);

endmodule