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view boards/mv-sniffer/src/ic_74LVC4T3144.v @ 13:82da4b7835b7

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FPGA Makefile: generate timing.rpt
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 01:12:16 +0000
parents 55e5f926fb5a
children
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module ic_74LVC4T3144 (GND, VccA, VccB, nOE, A1, A2, A3, YA4,
			YB1, YB2, YB3, B4);

input GND, VccA, VccB;
input nOE;
input A1, A2, A3, B4;
output YB1, YB2, YB3, YA4;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_TSSOP14 pkg (.pin_1(VccA),
		 .pin_2(A1),
		 .pin_3(A2),
		 .pin_4(A3),
		 .pin_5(YA4),
		 .pin_6(GND),
		 .pin_7(GND),
		 .pin_8(B4),
		 .pin_9(),	/* no connect */
		 .pin_10(YB3),
		 .pin_11(YB2),
		 .pin_12(YB1),
		 .pin_13(VccB),
		 .pin_14(nOE)
	);

endmodule