view fpga/tools/yosys-wrap @ 51:8a3003860cf8

doc/Sniffing-hw-setup: wire assignments for mv-sniffer setup
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 24 Sep 2023 01:15:44 +0000 (22 months ago)
parents af1a9732da1f
children
line wrap: on
line source
#!/bin/sh

if [ $# -lt 3 ]
then
	echo "usage: $0 top-module json-output verilog-src..." 1>&2
	exit 1
fi

top="$1"
json="$2"

shift
shift

rm -f "$json"
yosys -p "synth_ice40 -top $top -json $json" "$@"

if [ -f "$json" ]
then
	echo "$json created, declaring success"
	exit 0
else
	echo "$json NOT created, declaring error"
	exit 1
fi