FreeCalypso > hg > fc-sim-sniff
view fpga/tools/yosys-tee @ 58:95ed46b5f8f1 default tip
doc/Sniffing-hw-setup: mv-sniffer is here
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 04 Oct 2023 05:55:09 +0000 |
parents | cbfcc480d61b |
children |
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#!/bin/sh if [ $# -lt 4 ] then echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2 exit 1 fi top="$1" json="$2" report="$3" shift shift shift rm -f "$json" yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report" if [ -f "$json" ] then echo "$json created, declaring success" exit 0 else echo "$json NOT created, declaring error" exit 1 fi