FreeCalypso > hg > fc-sim-sniff

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FPGA build: include yosys-wrap in this repository
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 19:25:35 +0000
parents 00229623ca81
children c4346cdc9641
line wrap: on
line source

syntax: regexp

\.csv$
\.txt$
\.unet$
\.ps$
\.pdf$

\.asc$
\.bin$
\.json$
\.rpt$

^boards/mv-sniffer/pcb/gerbers\.
^boards/mv-sniffer/src/elements\.pcb$

^boards/sim-fpc-pasv/pcb/gerbers\.
^boards/sim-fpc-pasv/src/elements\.pcb$