module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
	    UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST_in, SIM_CLK_in,
	    SIM_IO_in, SIM_IO_out);

input CLK12;
output LED1, LED2, LED3, LED4, LED5;

input UART_TxD, UART_RTS, UART_DTR;
output UART_RxD, UART_CTS, UART_DSR, UART_DCD;

input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
output SIM_IO_out;

/* input synchronizers */

wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;

sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
		  SIM_IO_in, SIM_IO_sync);

/* character receiver */

wire Rx_strobe, Rx_error;
wire [7:0] Rx_char;
wire Rx_start_bit, Rx_parity_bit;

sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
		   Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);

/* explicit detection of RST transitions */

wire SIM_RST_toggle;

reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);

/* output to the host */

wire Tx_trigger;
wire [15:0] Tx_data;

assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,3'b000,
		  Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};

uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);

/* UART modem control outputs: unused */

assign UART_CTS = 1'b1;
assign UART_DSR = 1'b0;
assign UART_DCD = 1'b0;

/* board LEDs */

assign LED1 = 1'b1;
assign LED2 = 1'b0;
assign LED3 = 1'b1;
assign LED4 = 1'b0;
assign LED5 = SIM_RST_in;

/* SIM_IO_out dummy: if someone mistakenly connects an Icestick board with
 * this FPGA image in it to a cardem pod instead of the sniffing one,
 * we ensure that the 74LVC1G07 OD buffer remains off by feeding logic HIGH
 * to this buffer.
 */

assign SIM_IO_out = 1'b1;

endmodule