view fpga/sniffer-pps/spenh_ctrl.v @ 52:cbfcc480d61b

fpga build: migrate to yosys-tee wrapper
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 03 Oct 2023 18:17:58 +0000
parents ab37fcb71744
children
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/*
 * This module implements speed enhancement control based on signals
 * from the PPS catcher block.
 */

module spenh_ctrl (IntClk, SIM_RST_sync, Rx_strobe, Rx_char,
		   pos_PPS_resp_PPS1, pos_PPS_resp_PCK,
		   speed_enh_mode, speed_enh_mult);

input IntClk;
input SIM_RST_sync;
input Rx_strobe;
input [7:0] Rx_char;
input pos_PPS_resp_PPS1, pos_PPS_resp_PCK;

output reg speed_enh_mode;
output reg [1:0] speed_enh_mult;

always @(posedge IntClk)
	if (!SIM_RST_sync)
		speed_enh_mode <= 1'b0;
	else if (Rx_strobe && pos_PPS_resp_PCK)
		speed_enh_mode <= 1'b1;

always @(posedge IntClk)
	if (Rx_strobe && pos_PPS_resp_PPS1)
		speed_enh_mult <= Rx_char[1:0];

endmodule