FreeCalypso > hg > fc-sim-sniff
view fpga/tools/yosys-wrap @ 52:cbfcc480d61b
fpga build: migrate to yosys-tee wrapper
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Tue, 03 Oct 2023 18:17:58 +0000 |
parents | af1a9732da1f |
children |
line wrap: on
line source
#!/bin/sh if [ $# -lt 3 ] then echo "usage: $0 top-module json-output verilog-src..." 1>&2 exit 1 fi top="$1" json="$2" shift shift rm -f "$json" yosys -p "synth_ice40 -top $top -json $json" "$@" if [ -f "$json" ] then echo "$json created, declaring success" exit 0 else echo "$json NOT created, declaring error" exit 1 fi