module board ();

wire GND, VCC, VPP, RST, CLK, IO;

conn_6pin_plus2 fpc (.pin_1(VCC),
		     .pin_2(RST),
		     .pin_3(CLK),
		     .pin_4(IO),
		     .pin_5(VPP),
		     .pin_6(GND),
		     /* mounting pads */
		     .pin_7(GND),
		     .pin_8(GND)
	);

pkg_SIM_socket sim (.pin_1(VCC),
		    .pin_2(RST),
		    .pin_3(CLK),
		    .pin_4(),		/* gap in footprint pin numbering */
		    .pin_5(GND),
		    .pin_6(VPP),
		    .pin_7(IO),
		    .pin_8()		/* gap in footprint pin numbering */
	);

capacitor C1 (VCC, GND);

header_4pin tap_C1_C3 ( .pin_1(GND),
			.pin_2(VCC),	/* C1 */
			.pin_3(RST),	/* C2 */
			.pin_4(CLK)	/* C3 */
		);

header_4pin tap_C5_C7 ( .pin_1(GND),
			.pin_2(GND),	/* C5 */
			.pin_3(VPP),	/* C6 */
			.pin_4(IO)	/* C7 */
		);

endmodule