fc-sim-sniff: revision graph

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fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
Mon, 21 Aug 2023 01:07:26 +0000, by Mychaela Falconia
fpga/sniffer-basic/sniff_rx.v: typo in signal name
Mon, 21 Aug 2023 01:05:25 +0000, by Mychaela Falconia
FPGA Makefile: capture yosys stdout
Mon, 21 Aug 2023 01:00:16 +0000, by Mychaela Falconia
FPGA Makefile: yosys-wrap installed on Mother's system
Mon, 21 Aug 2023 00:55:33 +0000, by Mychaela Falconia

less more | rev 11: (0) -10 -4 +4 +10 +30 tip