FreeCalypso > hg > fc-sim-sniff
graph
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boards/mv-sniffer/pcb: add MakefileMon, 21 Aug 2023 03:03:41 +0000, by Mychaela Falconia
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boards/mv-sniffer: PCB layout doneMon, 21 Aug 2023 03:02:01 +0000, by Mychaela Falconia
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FPGA Makefile: generate timing.rptMon, 21 Aug 2023 01:12:16 +0000, by Mychaela Falconia
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FPGA Makefile: generate pnr.rptMon, 21 Aug 2023 01:10:23 +0000, by Mychaela Falconia
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fpga/sniffer-basic/top.v: correct SIM_RST polarity for LEDMon, 21 Aug 2023 01:07:26 +0000, by Mychaela Falconia
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fpga/sniffer-basic/sniff_rx.v: typo in signal nameMon, 21 Aug 2023 01:05:25 +0000, by Mychaela Falconia
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FPGA Makefile: capture yosys stdoutMon, 21 Aug 2023 01:00:16 +0000, by Mychaela Falconia
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FPGA Makefile: yosys-wrap installed on Mother's systemMon, 21 Aug 2023 00:55:33 +0000, by Mychaela Falconia