FreeCalypso > hg > fc-sim-sniff
graph
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FPGA Makefile: generate timing.rptMon, 21 Aug 2023 01:12:16 +0000, by Mychaela Falconia
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FPGA Makefile: generate pnr.rptMon, 21 Aug 2023 01:10:23 +0000, by Mychaela Falconia
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fpga/sniffer-basic/top.v: correct SIM_RST polarity for LEDMon, 21 Aug 2023 01:07:26 +0000, by Mychaela Falconia
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fpga/sniffer-basic/sniff_rx.v: typo in signal nameMon, 21 Aug 2023 01:05:25 +0000, by Mychaela Falconia
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FPGA Makefile: capture yosys stdoutMon, 21 Aug 2023 01:00:16 +0000, by Mychaela Falconia
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FPGA Makefile: yosys-wrap installed on Mother's systemMon, 21 Aug 2023 00:55:33 +0000, by Mychaela Falconia
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.hgignore: add FPGA build productsMon, 21 Aug 2023 00:54:09 +0000, by Mychaela Falconia
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fpga/sniffer-basic: initial versionMon, 21 Aug 2023 00:52:00 +0000, by Mychaela Falconia
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doc: add ISO7816-specs pointer articleSat, 29 Jul 2023 07:53:49 +0000, by Mychaela Falconia
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doc: describe proposed FPGA designSat, 29 Jul 2023 07:06:54 +0000, by Mychaela Falconia
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boards/mv-sniffer/src: generate elements.pcbFri, 28 Jul 2023 21:10:48 +0000, by Mychaela Falconia
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boards/mv-sniffer/src: components bound to MCLFri, 28 Jul 2023 20:17:52 +0000, by Mychaela Falconia
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beginning of mv-sniffer adapter board designFri, 28 Jul 2023 20:01:06 +0000, by Mychaela Falconia
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starting project with README and sim-fpc-pasv adapterMon, 17 Jul 2023 00:52:00 +0000, by Mychaela Falconia