fc-sim-sniff: revision graph

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fpga/sniffer-pps: add actual F/D control
Tue, 29 Aug 2023 21:22:37 +0000, by Mychaela Falconia
fpga/sniffer-*: forgot to change SIM_RST to SIM_RST_in for LED5
Tue, 29 Aug 2023 20:36:34 +0000, by Mychaela Falconia
fpga: add top Makefile across projects
Tue, 29 Aug 2023 20:35:51 +0000, by Mychaela Falconia
fpga/sniffer-pps: first version
Tue, 29 Aug 2023 20:05:23 +0000, by Mychaela Falconia
fpga tree: move icestick.pcf to common subdirectory
Tue, 29 Aug 2023 18:10:41 +0000, by Mychaela Falconia
fpga/sniffer-basic: drive pin 115 high for cardem pod
Tue, 29 Aug 2023 18:05:09 +0000, by Mychaela Falconia
doc/Sniffer-FPGA-design: update for working status
Tue, 29 Aug 2023 06:37:58 +0000, by Mychaela Falconia
doc/PPS-catcher-FSM: initial description
Tue, 22 Aug 2023 08:55:33 +0000, by Mychaela Falconia
sw/Makefile: add
Tue, 22 Aug 2023 06:29:27 +0000, by Mychaela Falconia
sw: simtrace3-sniff-rx program written, compiles
Tue, 22 Aug 2023 06:16:44 +0000, by Mychaela Falconia
sw/libserial: based on FC host tools version
Tue, 22 Aug 2023 02:44:23 +0000, by Mychaela Falconia
doc: on later thought, drop the DUS term in favor of ME/ID
Mon, 21 Aug 2023 20:14:26 +0000, by Mychaela Falconia
FPGA make clean: rm *.rpt too
Mon, 21 Aug 2023 19:26:24 +0000, by Mychaela Falconia
FPGA build: include yosys-wrap in this repository
Mon, 21 Aug 2023 19:25:35 +0000, by Mychaela Falconia
doc/Sniffer-FPGA-design: update for first implementation
Mon, 21 Aug 2023 06:50:55 +0000, by Mychaela Falconia
.hgignore: add mv-sniffer gerber files
Mon, 21 Aug 2023 03:09:34 +0000, by Mychaela Falconia
boards/mv-sniffer/pcb: add Makefile
Mon, 21 Aug 2023 03:03:41 +0000, by Mychaela Falconia
boards/mv-sniffer: PCB layout done
Mon, 21 Aug 2023 03:02:01 +0000, by Mychaela Falconia
FPGA Makefile: generate timing.rpt
Mon, 21 Aug 2023 01:12:16 +0000, by Mychaela Falconia
FPGA Makefile: generate pnr.rpt
Mon, 21 Aug 2023 01:10:23 +0000, by Mychaela Falconia
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
Mon, 21 Aug 2023 01:07:26 +0000, by Mychaela Falconia
fpga/sniffer-basic/sniff_rx.v: typo in signal name
Mon, 21 Aug 2023 01:05:25 +0000, by Mychaela Falconia
FPGA Makefile: capture yosys stdout
Mon, 21 Aug 2023 01:00:16 +0000, by Mychaela Falconia
FPGA Makefile: yosys-wrap installed on Mother's system
Mon, 21 Aug 2023 00:55:33 +0000, by Mychaela Falconia
.hgignore: add FPGA build products
Mon, 21 Aug 2023 00:54:09 +0000, by Mychaela Falconia
fpga/sniffer-basic: initial version
Mon, 21 Aug 2023 00:52:00 +0000, by Mychaela Falconia
doc: add ISO7816-specs pointer article
Sat, 29 Jul 2023 07:53:49 +0000, by Mychaela Falconia
doc: describe proposed FPGA design
Sat, 29 Jul 2023 07:06:54 +0000, by Mychaela Falconia
boards/mv-sniffer/src: generate elements.pcb
Fri, 28 Jul 2023 21:10:48 +0000, by Mychaela Falconia
boards/mv-sniffer/src: components bound to MCL
Fri, 28 Jul 2023 20:17:52 +0000, by Mychaela Falconia
beginning of mv-sniffer adapter board design
Fri, 28 Jul 2023 20:01:06 +0000, by Mychaela Falconia
starting project with README and sim-fpc-pasv adapter
Mon, 17 Jul 2023 00:52:00 +0000, by Mychaela Falconia

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