FreeCalypso > hg > fc-sim-sniff
graph
-
sw: simtrace3-sniff-rx program written, compilesTue, 22 Aug 2023 06:16:44 +0000, by Mychaela Falconia
-
sw/libserial: based on FC host tools versionTue, 22 Aug 2023 02:44:23 +0000, by Mychaela Falconia
-
doc: on later thought, drop the DUS term in favor of ME/IDMon, 21 Aug 2023 20:14:26 +0000, by Mychaela Falconia
-
FPGA make clean: rm *.rpt tooMon, 21 Aug 2023 19:26:24 +0000, by Mychaela Falconia
-
FPGA build: include yosys-wrap in this repositoryMon, 21 Aug 2023 19:25:35 +0000, by Mychaela Falconia
-
doc/Sniffer-FPGA-design: update for first implementationMon, 21 Aug 2023 06:50:55 +0000, by Mychaela Falconia
-
.hgignore: add mv-sniffer gerber filesMon, 21 Aug 2023 03:09:34 +0000, by Mychaela Falconia
-
boards/mv-sniffer/pcb: add MakefileMon, 21 Aug 2023 03:03:41 +0000, by Mychaela Falconia
-
boards/mv-sniffer: PCB layout doneMon, 21 Aug 2023 03:02:01 +0000, by Mychaela Falconia
-
FPGA Makefile: generate timing.rptMon, 21 Aug 2023 01:12:16 +0000, by Mychaela Falconia
-
FPGA Makefile: generate pnr.rptMon, 21 Aug 2023 01:10:23 +0000, by Mychaela Falconia
-
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LEDMon, 21 Aug 2023 01:07:26 +0000, by Mychaela Falconia
-
fpga/sniffer-basic/sniff_rx.v: typo in signal nameMon, 21 Aug 2023 01:05:25 +0000, by Mychaela Falconia
-
FPGA Makefile: capture yosys stdoutMon, 21 Aug 2023 01:00:16 +0000, by Mychaela Falconia
-
FPGA Makefile: yosys-wrap installed on Mother's systemMon, 21 Aug 2023 00:55:33 +0000, by Mychaela Falconia
-
.hgignore: add FPGA build productsMon, 21 Aug 2023 00:54:09 +0000, by Mychaela Falconia