FreeCalypso > hg > fc-sim-sniff
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doc/PPS-catcher-FSM: it has been implementedTue, 29 Aug 2023 22:58:26 +0000, by Mychaela Falconia
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sw/Makefile: add installTue, 29 Aug 2023 21:47:17 +0000, by Mychaela Falconia
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sw/sniff-rx/Makefile: add installTue, 29 Aug 2023 21:44:22 +0000, by Mychaela Falconia
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fpga/sniffer-pps: add actual F/D controlTue, 29 Aug 2023 21:22:37 +0000, by Mychaela Falconia
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fpga/sniffer-*: forgot to change SIM_RST to SIM_RST_in for LED5Tue, 29 Aug 2023 20:36:34 +0000, by Mychaela Falconia
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fpga: add top Makefile across projectsTue, 29 Aug 2023 20:35:51 +0000, by Mychaela Falconia
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fpga/sniffer-pps: first versionTue, 29 Aug 2023 20:05:23 +0000, by Mychaela Falconia
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fpga tree: move icestick.pcf to common subdirectoryTue, 29 Aug 2023 18:10:41 +0000, by Mychaela Falconia
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fpga/sniffer-basic: drive pin 115 high for cardem podTue, 29 Aug 2023 18:05:09 +0000, by Mychaela Falconia
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doc/Sniffer-FPGA-design: update for working statusTue, 29 Aug 2023 06:37:58 +0000, by Mychaela Falconia
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doc/PPS-catcher-FSM: initial descriptionTue, 22 Aug 2023 08:55:33 +0000, by Mychaela Falconia
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sw/Makefile: addTue, 22 Aug 2023 06:29:27 +0000, by Mychaela Falconia
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sw: simtrace3-sniff-rx program written, compilesTue, 22 Aug 2023 06:16:44 +0000, by Mychaela Falconia
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sw/libserial: based on FC host tools versionTue, 22 Aug 2023 02:44:23 +0000, by Mychaela Falconia
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doc: on later thought, drop the DUS term in favor of ME/IDMon, 21 Aug 2023 20:14:26 +0000, by Mychaela Falconia
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FPGA make clean: rm *.rpt tooMon, 21 Aug 2023 19:26:24 +0000, by Mychaela Falconia
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FPGA build: include yosys-wrap in this repositoryMon, 21 Aug 2023 19:25:35 +0000, by Mychaela Falconia
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doc/Sniffer-FPGA-design: update for first implementationMon, 21 Aug 2023 06:50:55 +0000, by Mychaela Falconia
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.hgignore: add mv-sniffer gerber filesMon, 21 Aug 2023 03:09:34 +0000, by Mychaela Falconia
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boards/mv-sniffer/pcb: add MakefileMon, 21 Aug 2023 03:03:41 +0000, by Mychaela Falconia
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boards/mv-sniffer: PCB layout doneMon, 21 Aug 2023 03:02:01 +0000, by Mychaela Falconia
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FPGA Makefile: generate timing.rptMon, 21 Aug 2023 01:12:16 +0000, by Mychaela Falconia
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FPGA Makefile: generate pnr.rptMon, 21 Aug 2023 01:10:23 +0000, by Mychaela Falconia
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fpga/sniffer-basic/top.v: correct SIM_RST polarity for LEDMon, 21 Aug 2023 01:07:26 +0000, by Mychaela Falconia
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fpga/sniffer-basic/sniff_rx.v: typo in signal nameMon, 21 Aug 2023 01:05:25 +0000, by Mychaela Falconia
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FPGA Makefile: capture yosys stdoutMon, 21 Aug 2023 01:00:16 +0000, by Mychaela Falconia
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FPGA Makefile: yosys-wrap installed on Mother's systemMon, 21 Aug 2023 00:55:33 +0000, by Mychaela Falconia
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.hgignore: add FPGA build productsMon, 21 Aug 2023 00:54:09 +0000, by Mychaela Falconia
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fpga/sniffer-basic: initial versionMon, 21 Aug 2023 00:52:00 +0000, by Mychaela Falconia
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doc: add ISO7816-specs pointer articleSat, 29 Jul 2023 07:53:49 +0000, by Mychaela Falconia
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doc: describe proposed FPGA designSat, 29 Jul 2023 07:06:54 +0000, by Mychaela Falconia
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boards/mv-sniffer/src: generate elements.pcbFri, 28 Jul 2023 21:10:48 +0000, by Mychaela Falconia
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boards/mv-sniffer/src: components bound to MCLFri, 28 Jul 2023 20:17:52 +0000, by Mychaela Falconia
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beginning of mv-sniffer adapter board designFri, 28 Jul 2023 20:01:06 +0000, by Mychaela Falconia
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starting project with README and sim-fpc-pasv adapterMon, 17 Jul 2023 00:52:00 +0000, by Mychaela Falconia