FreeCalypso > hg > fc-sim-sniff
graph
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FPGA make clean: rm *.rpt too19 months ago, by Mychaela Falconia
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FPGA build: include yosys-wrap in this repository19 months ago, by Mychaela Falconia
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doc/Sniffer-FPGA-design: update for first implementation19 months ago, by Mychaela Falconia
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.hgignore: add mv-sniffer gerber files19 months ago, by Mychaela Falconia
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boards/mv-sniffer/pcb: add Makefile19 months ago, by Mychaela Falconia
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boards/mv-sniffer: PCB layout done19 months ago, by Mychaela Falconia
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FPGA Makefile: generate timing.rpt19 months ago, by Mychaela Falconia
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FPGA Makefile: generate pnr.rpt19 months ago, by Mychaela Falconia
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fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED19 months ago, by Mychaela Falconia
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fpga/sniffer-basic/sniff_rx.v: typo in signal name19 months ago, by Mychaela Falconia
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FPGA Makefile: capture yosys stdout19 months ago, by Mychaela Falconia
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FPGA Makefile: yosys-wrap installed on Mother's system19 months ago, by Mychaela Falconia
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.hgignore: add FPGA build products19 months ago, by Mychaela Falconia
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fpga/sniffer-basic: initial version19 months ago, by Mychaela Falconia
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doc: add ISO7816-specs pointer article20 months ago, by Mychaela Falconia
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doc: describe proposed FPGA design20 months ago, by Mychaela Falconia
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boards/mv-sniffer/src: generate elements.pcb20 months ago, by Mychaela Falconia
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boards/mv-sniffer/src: components bound to MCL20 months ago, by Mychaela Falconia
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beginning of mv-sniffer adapter board design20 months ago, by Mychaela Falconia
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starting project with README and sim-fpc-pasv adapter21 months ago, by Mychaela Falconia