# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1692579616 0
# Node ID 10c779b8753e8262cffa90ebca59beb7f381102b
# Parent  7cab8e0dd937927294a39a810be95daf47f165f5
FPGA Makefile: capture yosys stdout

diff -r 7cab8e0dd937 -r 10c779b8753e fpga/sniffer-basic/Makefile
--- a/fpga/sniffer-basic/Makefile	Mon Aug 21 00:55:33 2023 +0000
+++ b/fpga/sniffer-basic/Makefile	Mon Aug 21 01:00:16 2023 +0000
@@ -5,7 +5,7 @@
 all:	${PROJ}.bin
 
 ${PROJ}.json:	${VSRC}
-	yosys-wrap top $@ ${VSRC}
+	yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
 
 ${PROJ}.asc:	${PROJ}.json ${PCF}
 	nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \