# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1690574466 0
# Node ID 55e5f926fb5ab0064d5b5c309e6eb31683180913
# Parent  fbbafa93b52b3cd096599504a00b99752e748153
beginning of mv-sniffer adapter board design

diff -r fbbafa93b52b -r 55e5f926fb5a .hgignore
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/.hgignore	Fri Jul 28 20:01:06 2023 +0000
@@ -0,0 +1,10 @@
+syntax: regexp
+
+\.csv$
+\.txt$
+\.unet$
+\.ps$
+\.pdf$
+
+^boards/sim-fpc-pasv/pcb/gerbers\.
+^boards/sim-fpc-pasv/src/elements\.pcb$
diff -r fbbafa93b52b -r 55e5f926fb5a boards/mv-sniffer/src/MCL
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/mv-sniffer/src/MCL	Fri Jul 28 20:01:06 2023 +0000
@@ -0,0 +1,58 @@
+part cap-0603-100n:
+ value=100n
+ footprint=0603
+ description=Ceramic chip capacitor, X7R, 0.1 uF, 0603
+ manufacturer=Samsung Electro-Mechanics
+ manufacturer_part_number=CL10B104KB8NNWC
+ vendor=Digi-Key
+ vendor_part_number=1276-1935-1-ND
+ npins=2
+
+C1:
+ part=cap-0603-100n
+
+C2:
+ part=cap-0603-100n
+
+part header-6pin:
+ footprint=JUMPER6
+ description=Header, 0.100", single row, 6 posts
+ manufacturer=Molex
+ manufacturer_part_number=0901200926
+ vendor=Digi-Key
+ vendor_part_number=WM14728-ND
+ npins=6
+
+J1:
+ part=header-6pin
+
+J2:
+ part=header-6pin
+
+part res-0603-47k:
+ value=47k
+ footprint=0603
+ description=Chip resistor, 47 kOhm, 0603
+ manufacturer=Yageo
+ manufacturer_part_number=RC0603FR-1347KL
+ vendor=Digi-Key
+ vendor_part_number=13-RC0603FR-1347KLCT-ND
+ npins=2
+
+R1:
+ part=res-0603-47k
+
+R2:
+ part=res-0603-47k
+
+R3:
+ part=res-0603-47k
+
+U1:
+ device=74LVC4T3144
+ manufacturer=Nexperia
+ manufacturer_part_number=74LVC4T3144PWJ
+ description=Dual supply buffer IC, TSSOP14
+ vendor=Digi-Key
+ vendor_part_number=1727-7424-1-ND
+ npins=14
diff -r fbbafa93b52b -r 55e5f926fb5a boards/mv-sniffer/src/Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/mv-sniffer/src/Makefile	Fri Jul 28 20:01:06 2023 +0000
@@ -0,0 +1,28 @@
+BOMS=	tallied-bom.txt tallied-bom.csv comptab.txt
+NETS=	sverp.unet #bound.unet pcb-netlist.txt
+
+all:	${BOMS} ${NETS} #elements.pcb
+
+sverp.unet:	schem.v ic_74LVC4T3144.v primitives
+	ueda-sverp -o $@ schem.v ic_74LVC4T3144.v
+
+bound.unet:	MCL sverp.unet
+	unet-bind -c sverp.unet $@
+
+pcb-netlist.txt:	bound.unet
+	unet2pcb bound.unet $@
+
+tallied-bom.txt:	MCL
+	ueda-mkbom -cr > $@
+
+tallied-bom.csv:	MCL
+	ueda-csvbom > $@
+
+comptab.txt:	MCL
+	ueda-shortbom > $@
+
+elements.pcb:	MCL
+	ueda-getfps -ch | ueda-runm4 > $@
+
+clean:
+	rm -f *.unet *.txt *.csv errs elements.pcb
diff -r fbbafa93b52b -r 55e5f926fb5a boards/mv-sniffer/src/ic_74LVC4T3144.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/mv-sniffer/src/ic_74LVC4T3144.v	Fri Jul 28 20:01:06 2023 +0000
@@ -0,0 +1,27 @@
+module ic_74LVC4T3144 (GND, VccA, VccB, nOE, A1, A2, A3, YA4,
+			YB1, YB2, YB3, B4);
+
+input GND, VccA, VccB;
+input nOE;
+input A1, A2, A3, B4;
+output YB1, YB2, YB3, YA4;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_TSSOP14 pkg (.pin_1(VccA),
+		 .pin_2(A1),
+		 .pin_3(A2),
+		 .pin_4(A3),
+		 .pin_5(YA4),
+		 .pin_6(GND),
+		 .pin_7(GND),
+		 .pin_8(B4),
+		 .pin_9(),	/* no connect */
+		 .pin_10(YB3),
+		 .pin_11(YB2),
+		 .pin_12(YB1),
+		 .pin_13(VccB),
+		 .pin_14(nOE)
+	);
+
+endmodule
diff -r fbbafa93b52b -r 55e5f926fb5a boards/mv-sniffer/src/primitives
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/mv-sniffer/src/primitives	Fri Jul 28 20:01:06 2023 +0000
@@ -0,0 +1,9 @@
+/* passives */
+capacitor	numpins 2;
+resistor	numpins 2;
+
+/* connectors */
+header_6pin	numpins 6;
+
+/* sniffing buffer IC: 74LVC4T3144 */
+pkg_TSSOP14	numpins 14;
diff -r fbbafa93b52b -r 55e5f926fb5a boards/mv-sniffer/src/schem.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/mv-sniffer/src/schem.v	Fri Jul 28 20:01:06 2023 +0000
@@ -0,0 +1,52 @@
+module board ();
+
+wire GND;
+wire SIM_VCC, SIM_RST, SIM_CLK, SIM_IO;
+wire FPGA_VCC, FPGA_RST, FPGA_CLK, FPGA_IO;
+
+/* headers connecting to other boards */
+
+header_6pin hdr_sim (.pin_1(SIM_VCC),
+		     .pin_2(SIM_RST),
+		     .pin_3(SIM_CLK),
+		     .pin_4(SIM_IO),
+		     .pin_5(GND),
+		     .pin_6(GND)
+	);
+
+header_6pin hdr_fpga (.pin_1(FPGA_VCC),
+		      .pin_2(GND),
+		      .pin_3(FPGA_RST),
+		      .pin_4(FPGA_CLK),
+		      .pin_5(FPGA_IO),
+		      .pin_6()		/* unused */
+	);
+
+/* sniffing buffer IC */
+
+ic_74LVC4T3144 buffer ( .GND(GND),
+			.VccA(SIM_VCC),
+			.VccB(FPGA_VCC),
+			.nOE(GND),
+			.A1(SIM_RST),
+			.A2(SIM_CLK),
+			.A3(SIM_IO),
+			.YA4(),		/* no connect */
+			.YB1(FPGA_RST),
+			.YB2(FPGA_CLK),
+			.YB3(FPGA_IO),
+			.B4(GND)
+	);
+
+/* bypass caps next to buffer IC supply pins */
+
+capacitor C1 (SIM_VCC, GND);
+capacitor C2 (FPGA_VCC, GND);
+
+/* pull-down resistors on buffer IC outputs, for PPD mode */
+
+resistor R1 (FPGA_RST, GND);
+resistor R2 (FPGA_CLK, GND);
+resistor R3 (FPGA_IO, GND);
+
+endmodule