# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1696361729 0
# Node ID 737579209153211989c816dca7d9a57a39379e8a
# Parent  cbfcc480d61b6c343c6fd88536ff0b269b219b40
fpga/sniffer-pps: add LED indication of running SIM CLK

diff -r cbfcc480d61b -r 737579209153 fpga/sniffer-pps/Makefile
--- a/fpga/sniffer-pps/Makefile	Tue Oct 03 18:17:58 2023 +0000
+++ b/fpga/sniffer-pps/Makefile	Tue Oct 03 19:35:29 2023 +0000
@@ -1,5 +1,5 @@
-VSRC=	clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v spenh_ctrl.v \
-	sync_inputs.v top.v uart_tx.v
+VSRC=	clk_check.v clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v \
+	spenh_ctrl.v sync_inputs.v top.v uart_tx.v
 PCF=	../common/icestick.pcf
 PROJ=	fpga
 
diff -r cbfcc480d61b -r 737579209153 fpga/sniffer-pps/clk_check.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/sniffer-pps/clk_check.v	Tue Oct 03 19:35:29 2023 +0000
@@ -0,0 +1,19 @@
+/*
+ * The logic implemented in this module detects if SIM_CLK is running or not,
+ * for the purpose of visual indication on a LED.
+ */
+
+module clk_check (IntClk, SIM_CLK_sync, SIM_CLK_running);
+
+input IntClk;
+input SIM_CLK_sync;
+output SIM_CLK_running;
+
+reg [11:0] shift_reg;
+
+always @(posedge IntClk)
+	shift_reg <= {shift_reg[10:0],SIM_CLK_sync};
+
+assign SIM_CLK_running = (shift_reg != 12'h000) && (shift_reg != 12'hFFF);
+
+endmodule
diff -r cbfcc480d61b -r 737579209153 fpga/sniffer-pps/top.v
--- a/fpga/sniffer-pps/top.v	Tue Oct 03 18:17:58 2023 +0000
+++ b/fpga/sniffer-pps/top.v	Tue Oct 03 19:35:29 2023 +0000
@@ -18,6 +18,12 @@
 sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
 		  SIM_IO_in, SIM_IO_sync);
 
+/* running clock detector */
+
+wire SIM_CLK_running;
+
+clk_check clk_check (CLK12, SIM_CLK_sync, SIM_CLK_running);
+
 /* character receiver */
 
 wire Rx_strobe, Rx_error;
@@ -69,7 +75,7 @@
 /* board LEDs */
 
 assign LED1 = 1'b1;
-assign LED2 = 1'b0;
+assign LED2 = SIM_CLK_running;
 assign LED3 = 1'b1;
 assign LED4 = 1'b0;
 assign LED5 = SIM_RST_in;