# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1693332641 0
# Node ID 990ecafdddb4a869ba2c72aaba75cf3fff49e360
# Parent  e5c5162b3a8cc23f72f10a0158f02ae8a512d5d0
fpga tree: move icestick.pcf to common subdirectory

diff -r e5c5162b3a8c -r 990ecafdddb4 fpga/common/icestick.pcf
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/common/icestick.pcf	Tue Aug 29 18:10:41 2023 +0000
@@ -0,0 +1,29 @@
+# Pin Constraint File for the HK1X FPGA as wired on the Icestick board,
+# adapted for SIMtrace-ice application.
+
+# Board essentials
+set_io	CLK12		21
+set_io	LED1		99
+set_io	LED2		98
+set_io	LED3		97
+set_io	LED4		96
+set_io	LED5		95
+
+# FT2232H UART channel, signal names are from FT2232H DTE perspective,
+# the logic in the FPGA has to act as DCE.
+
+set_io	UART_TxD	9
+set_io	UART_RxD	8
+set_io	UART_RTS	7
+set_io	UART_CTS	4
+set_io	UART_DTR	3
+set_io	UART_DSR	2
+set_io	UART_DCD	1
+
+# SIM sniffing interface, receiving outputs from the level shifter board
+# via J1 header pins, plus output line for OD buffer in cardem application.
+
+set_io	SIM_RST_in	112
+set_io	SIM_CLK_in	113
+set_io	SIM_IO_in	114
+set_io	SIM_IO_out	115
diff -r e5c5162b3a8c -r 990ecafdddb4 fpga/sniffer-basic/Makefile
--- a/fpga/sniffer-basic/Makefile	Tue Aug 29 18:05:09 2023 +0000
+++ b/fpga/sniffer-basic/Makefile	Tue Aug 29 18:10:41 2023 +0000
@@ -1,5 +1,5 @@
 VSRC=	clk_edge.v reset_detect.v sniff_rx.v sync_inputs.v top.v uart_tx.v
-PCF=	icestick.pcf
+PCF=	../common/icestick.pcf
 PROJ=	fpga
 
 all:	${PROJ}.bin timing.rpt
diff -r e5c5162b3a8c -r 990ecafdddb4 fpga/sniffer-basic/icestick.pcf
--- a/fpga/sniffer-basic/icestick.pcf	Tue Aug 29 18:05:09 2023 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,29 +0,0 @@
-# Pin Constraint File for the HK1X FPGA as wired on the Icestick board,
-# adapted for SIMtrace-ice application.
-
-# Board essentials
-set_io	CLK12		21
-set_io	LED1		99
-set_io	LED2		98
-set_io	LED3		97
-set_io	LED4		96
-set_io	LED5		95
-
-# FT2232H UART channel, signal names are from FT2232H DTE perspective,
-# the logic in the FPGA has to act as DCE.
-
-set_io	UART_TxD	9
-set_io	UART_RxD	8
-set_io	UART_RTS	7
-set_io	UART_CTS	4
-set_io	UART_DTR	3
-set_io	UART_DSR	2
-set_io	UART_DCD	1
-
-# SIM sniffing interface, receiving outputs from the level shifter board
-# via J1 header pins, plus output line for OD buffer in cardem application.
-
-set_io	SIM_RST_in	112
-set_io	SIM_CLK_in	113
-set_io	SIM_IO_in	114
-set_io	SIM_IO_out	115