# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1692645935 0
# Node ID af1a9732da1f22875fe96bd286bc454316d13e33
# Parent  41e6026e5d1a8cc855a8dec63ce33da7122f6354
FPGA build: include yosys-wrap in this repository

diff -r 41e6026e5d1a -r af1a9732da1f fpga/sniffer-basic/Makefile
--- a/fpga/sniffer-basic/Makefile	Mon Aug 21 06:50:55 2023 +0000
+++ b/fpga/sniffer-basic/Makefile	Mon Aug 21 19:25:35 2023 +0000
@@ -5,7 +5,7 @@
 all:	${PROJ}.bin timing.rpt
 
 ${PROJ}.json:	${VSRC}
-	yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
+	../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
 
 ${PROJ}.asc:	${PROJ}.json ${PCF}
 	nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
diff -r 41e6026e5d1a -r af1a9732da1f fpga/tools/yosys-wrap
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/tools/yosys-wrap	Mon Aug 21 19:25:35 2023 +0000
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+if [ $# -lt 3 ]
+then
+	echo "usage: $0 top-module json-output verilog-src..." 1>&2
+	exit 1
+fi
+
+top="$1"
+json="$2"
+
+shift
+shift
+
+rm -f "$json"
+yosys -p "synth_ice40 -top $top -json $json" "$@"
+
+if [ -f "$json" ]
+then
+	echo "$json created, declaring success"
+	exit 0
+else
+	echo "$json NOT created, declaring error"
+	exit 1
+fi