# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1696357078 0
# Node ID cbfcc480d61b6c343c6fd88536ff0b269b219b40
# Parent  8a3003860cf89381b9570d01419a7a56ee323d17
fpga build: migrate to yosys-tee wrapper

diff -r 8a3003860cf8 -r cbfcc480d61b fpga/sniffer-basic/Makefile
--- a/fpga/sniffer-basic/Makefile	Sun Sep 24 01:15:44 2023 +0000
+++ b/fpga/sniffer-basic/Makefile	Tue Oct 03 18:17:58 2023 +0000
@@ -5,7 +5,7 @@
 all:	${PROJ}.bin timing.rpt
 
 ${PROJ}.json:	${VSRC}
-	../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
+	../tools/yosys-tee top $@ synthesis.rpt ${VSRC}
 
 ${PROJ}.asc:	${PROJ}.json ${PCF}
 	nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
diff -r 8a3003860cf8 -r cbfcc480d61b fpga/sniffer-pps/Makefile
--- a/fpga/sniffer-pps/Makefile	Sun Sep 24 01:15:44 2023 +0000
+++ b/fpga/sniffer-pps/Makefile	Tue Oct 03 18:17:58 2023 +0000
@@ -6,7 +6,7 @@
 all:	${PROJ}.bin timing.rpt
 
 ${PROJ}.json:	${VSRC}
-	../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
+	../tools/yosys-tee top $@ synthesis.rpt ${VSRC}
 
 ${PROJ}.asc:	${PROJ}.json ${PCF}
 	nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
diff -r 8a3003860cf8 -r cbfcc480d61b fpga/tools/yosys-tee
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/tools/yosys-tee	Tue Oct 03 18:17:58 2023 +0000
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+if [ $# -lt 4 ]
+then
+	echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2
+	exit 1
+fi
+
+top="$1"
+json="$2"
+report="$3"
+
+shift
+shift
+shift
+
+rm -f "$json"
+yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report"
+
+if [ -f "$json" ]
+then
+	echo "$json created, declaring success"
+	exit 0
+else
+	echo "$json NOT created, declaring error"
+	exit 1
+fi