# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1693332309 0
# Node ID e5c5162b3a8cc23f72f10a0158f02ae8a512d5d0
# Parent  c03a882cc49ebbb2e1e5e5cd0c4f6f4a16571f15
fpga/sniffer-basic: drive pin 115 high for cardem pod

diff -r c03a882cc49e -r e5c5162b3a8c fpga/sniffer-basic/icestick.pcf
--- a/fpga/sniffer-basic/icestick.pcf	Tue Aug 29 06:37:58 2023 +0000
+++ b/fpga/sniffer-basic/icestick.pcf	Tue Aug 29 18:05:09 2023 +0000
@@ -21,8 +21,9 @@
 set_io	UART_DCD	1
 
 # SIM sniffing interface, receiving outputs from the level shifter board
-# via J1 header pins
+# via J1 header pins, plus output line for OD buffer in cardem application.
 
-set_io	SIM_RST		112
-set_io	SIM_CLK		113
-set_io	SIM_IO		114
+set_io	SIM_RST_in	112
+set_io	SIM_CLK_in	113
+set_io	SIM_IO_in	114
+set_io	SIM_IO_out	115
diff -r c03a882cc49e -r e5c5162b3a8c fpga/sniffer-basic/top.v
--- a/fpga/sniffer-basic/top.v	Tue Aug 29 06:37:58 2023 +0000
+++ b/fpga/sniffer-basic/top.v	Tue Aug 29 18:05:09 2023 +0000
@@ -1,5 +1,6 @@
 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
-	    UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST, SIM_CLK, SIM_IO);
+	    UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST_in, SIM_CLK_in,
+	    SIM_IO_in, SIM_IO_out);
 
 input CLK12;
 output LED1, LED2, LED3, LED4, LED5;
@@ -7,14 +8,15 @@
 input UART_TxD, UART_RTS, UART_DTR;
 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
 
-input SIM_RST, SIM_CLK, SIM_IO;
+input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
+output SIM_IO_out;
 
 /* input synchronizers */
 
 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
 
-sync_inputs sync (CLK12, SIM_RST, SIM_RST_sync, SIM_CLK, SIM_CLK_sync,
-		  SIM_IO, SIM_IO_sync);
+sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
+		  SIM_IO_in, SIM_IO_sync);
 
 /* character receiver */
 
@@ -56,4 +58,12 @@
 assign LED4 = 1'b0;
 assign LED5 = SIM_RST;
 
+/* SIM_IO_out dummy: if someone mistakenly connects an Icestick board with
+ * this FPGA image in it to a cardem pod instead of the sniffing one,
+ * we ensure that the 74LVC1G07 OD buffer remains off by feeding logic HIGH
+ * to this buffer.
+ */
+
+assign SIM_IO_out = 1'b1;
+
 endmodule