--- a/doc/Sniffer-FPGA-design	Tue Aug 22 08:55:33 2023 +0000
+++ b/doc/Sniffer-FPGA-design	Tue Aug 29 06:37:58 2023 +0000
@@ -1,16 +1,13 @@
-The first FPGA logic function in the SIMtrace-ice project has been implemented
-and is now waiting to be tested: it is the basic sniffer FPGA in the
-fpga/sniffer-basic directory.  It is an FPGA image for Lattice Icestick, an
-inexpensive off-the-shelf iCE40 FPGA board, and it implements the function of
-passive sniffing: receiving level-shifted SIM RST, CLK and I/O signals from the
-74LVC4T3144 buffer and capturing all exchanges that happen on the SIM interface
-between a GSM ME or other interface device (ME/ID for short) and a SIM.
+The first version of SIMtrace3 sniffer FPGA (the version in fpga/sniffer-basic,
+no PPS catcher, F/D=372 only for now) has been implemented, tested and proven
+working.  It is an FPGA image for Lattice Icestick, an inexpensive off-the-shelf
+iCE40 FPGA board, and it implements the function of passive sniffing: receiving
+level-shifted SIM RST, CLK and I/O signals from the 74LVC4T3144 buffer and
+capturing all exchanges that happen on the SIM interface between a GSM ME or
+other interface device (ME/ID for short) and a SIM.
 
-This FPGA gateware function is currently waiting to be tested: some custom
-hardware needs to be assembled before the FPGA can be tested.  The PCB fab order
-for our mv-sniffer adapter board has just been placed; we will need to receive
-the PCB, get it populated, and also populate the missing pin headers on the
-Icestick board before we can test our FPGA.
+Hardware architecture and FPGA design principle
+===============================================
 
 The two principal components of the Icestick board are an iCE40HX1K FPGA and an
 FT2232H-based USB host interface.  Our sniffer logic function in the FPGA