FreeCalypso > hg > fc-sim-sniff

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starting project with README and sim-fpc-pasv adapter
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jul 2023 00:52:00 +0000
parents
children 55e5f926fb5a
files README boards/sim-fpc-pasv/pcb/Makefile boards/sim-fpc-pasv/pcb/sim-fpc-pasv.pcb boards/sim-fpc-pasv/src/MCL boards/sim-fpc-pasv/src/Makefile boards/sim-fpc-pasv/src/primitives boards/sim-fpc-pasv/src/schem.v
diffstat 7 files changed, 1265 insertions(+), 0 deletions(-) [+]
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/README	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,150 @@
+Alternative implementation of SIMtrace idea,
+using iCE40 FPGA instead of AT91SAMx
+============================================
+
+Q: What is the principal idea behind SIMtrace, as distinct from the specific
+implementation realized by "standard" Osmocom SIMtrace?
+
+A: The two principal objectives of SIMtrace are:
+
+1) Passive sniffing of communication between a phone-type device and a SIM,
+   ideally as transparent and non-invasive as possible.
+
+2) Card emulation: the SIMtrace apparatus presents itself to the phone (or
+   modem or other phone-type device) as a SIM, either emulating the entire
+   SIM CardOS functionality in software or communicating with a real SIM
+   located somewhere remotely, across the Internet.
+
+Q: What are the shortcomings of the existing Osmocom SIMtrace implementation of
+   the above goals?
+
+A: In the opinion of Mother Mychaela of FreeCalypso, the electrical aspects of
+   Osmocom SIMtrace implementation are its biggest shortcoming.  The following
+   problems are most acute currently:
+
+* Current SIMtrace v2 hardware is not 5V-tolerant: connecting this apparatus to
+  an old phone that puts out 5V (class A) on its SIM socket can damage the
+  hardware, as class A SIM voltages exceed the absolute maximum rating spec of
+  the AT91SAM3S4B microcontroller on the SIMtrace v2 board, which is connected
+  directly to the SIM bus.
+
+* One option would be to revive the previous hardware generation as in SIMtrace
+  v1, replacing the AT91SAM3S with AT91SAM7S.  However, all firmware maintained
+  by Osmocom is written for SAM3S only, thus a backport to SAM7S would involve
+  significant work.  Given that the resulting solution would still be far from
+  my idea of perfection, I find it difficult to justify investing in that
+  software effort - instead I would rather work on a more philosophically-proper
+  solution.
+
+* AT91SAMx-based SIMtrace, both v1 and v2, works (most of the time, but not 100%
+  reliably) with 1.8V phone-SIM combination (a phone that prefers class C and a
+  SIM that supports it) only by accident.  The Vih spec (the minimum required
+  voltage on a signal line for it to register reliably as a 1) is 2.0 V for
+  AT91SAM7S or 2.31 V (0.7 * Vddio, Vddio = 3.3 V) for AT91SAM3S, but the actual
+  voltage on SIM interface lines in class C operation will never rise above
+  1.8 V.  The electrical interface on this hw operates severely out of spec,
+  and I find it rather miraculous that it works at all.  Not surprisingly,
+  reports are starting to trickle in with user experiences of it actually NOT
+  working sometimes.
+
+* Even if the SIM interface is restricted (by the phone, by the SIM, or by
+  SIMtrace MITM function tampering with ATR or file characteristics bytes) to
+  operating in class B (3.0 V nominal) only, the existing AT91SAMx SIMtrace
+  boards are still electrically unclean.  Looking at the schematics, one can see
+  that both CLK and I/O lines are pulled up (with resistors) to the SIMtrace
+  board's 3.3V rail, which is a higher voltage that what the phone will put out
+  (3.0 V or 1.8 V), and in the case of SIMtrace v1 with a 5V phone, that pull-up
+  will turn into a pull-midway-down instead.
+
+* My philosophy is that the tracing apparatus should be making only a high-
+  impedance connection to the SIM bus and nothing more, while the SIM bus itself
+  is galvanically connected from the phone to the physical SIM without passing
+  through any switches or other potential Heisenbug-inducing artifacts.
+
+My first thought was to gently modify the existing AT91SAMx-based SIMtrace
+design for electrically clean multivolt operation:
+
+* Replace the electrical switches for SIM VCC (FPF2109) and SIM RST/CLK/IO
+  (CB3Q3244) with either a relay (my initial thought, but way too power-hungry)
+  or a manually operated 5PDT slide switch;
+
+* Insert a Nexperia 74LVC4T3144 dual-supply buffer between the SIM bus and the
+  MCU, providing a sniffing path that not only supports all 3 voltage classes,
+  but is electrically clean, making only a high-impedance connection to the SIM
+  bus as I desire;
+
+* Connect a 74LVC1G07 open drain driver (fed with TxD from the MCU) to the SIM
+  bus I/O line, providing a signal path for card emulation mode.  (In trace mode
+  the firmware would be responsible for never turning on this OD driver, keeping
+  the tracing apparatus High-Z.)
+
+However, as I was reading AT91SAMx datasheets more carefully in preparation for
+embarking on a project to turn the above idea into reality, I saw a big problem:
+when the USART is put into ISO 7816-3 mode, it uses the chip's TxD pin (switched
+to open drain operation) for both Rx and Tx, and there is no option to keep
+separate RxD and TxD pins with an external receiving buffer and an external OD
+driver.
+
+It would probably be possible to build an all-voltage SIM interface with
+AT91SAMx, perhaps by using one of those bidirectional level shifter ICs that
+somehow automagically handle driving direction reversals.  But I personally am
+not too inclined to trust those automagical bidirectional translators, they
+just don't align with my design philosophy - I would much much rather have
+unidirectional buffers, one for sniffing and another for OD-driving the I/O
+line in card emulation mode.  Seeing that AT91SAMx is incompatible with such
+electrical design, I decided to screw AT91SAMx and go for a radically different
+approach.
+
+Outline of FPGA-based alternative design
+========================================
+
+My (Mother Mychaela's) idea of alternative SIMtrace implementation consists of
+the following pieces:
+
+1) The passive SIMtrace FPC connection board (boards/sim-fpc-pasv) is a trivial
+   PCB that electrically interconnects a SIM socket, an FPC connection for
+   SIMtrace FPC cables and a set of 2.54 mm header pins bringing out all SIM
+   interface signals.
+
+2) A second little adapter board (tentatively named mv-sniffer) will feature one
+   active component, but will still be just as trivial: it will be a PCB hosting
+   a single 74LVC4T3144 IC, with 2.54 mm header pins for the SIM side (SIM VCC
+   will go to the buffer IC's VccA) and for the FPGA board side; a power rail
+   from the latter board will go to the buffer IC's VccB.
+
+3) The FPGA board will be an off-the-shelf item, eliminating the major hurdle
+   of having to design and build a custom board of substantial complexity.  My
+   first attempt will be to use the Icestick board with iCE40HX1K FPGA; if this
+   FPGA proves to be too small, I will then look for another suitable board
+   with a bigger FPGA.
+
+The Icestick board features not only the HX1K FPGA, but also an FT2232H chip
+handling the USB interface.  FT2232H channel A is for FPGA programming, but
+channel B is a regular UART, connected with PCB traces to FPGA I/O pins for
+user logic.  The logic implemented in the FPGA will use this UART interface to
+communicate with higher-level software, which will be implemented as simple
+userspace programs - thus there is no "firmware" component per se.
+
+In terms of FPGA gateware functionality, the passive sniffer function will be
+implemented first; once it works, a different logic design will be implemented
+for card emulation mode.
+
+In terms of hardware as in boards, the first prototype version will use separate
+sim-fpc-pasv and mv-sniffer boards, connected with jumper wires between 2.54 mm
+header pins.  Because the signals carried by these jumper wires reside on the
+"target" SIM bus side of the buffer, these wires add more than just clutter -
+they also add to the electrical length of the external SIM bus, which is
+obviously bad.  Once the basic design is proven good, I plan to spin out another
+simple board that will feature the SIM socket, the SIMtrace FPC connector, the
+74LVC4T3144 buffer and a header for connecting to the FPGA board.  Because the
+latter connection resides past the buffer, wire length here does NOT add to the
+SIM bus.
+
+All of the just-described hardware config is for tracing only, not for card
+emulation.  For the latter function yet another, albeit still very simple,
+adapter board will need to be made.  The cardem adapter board will feature the
+SIMtrace FPC connector, two active ICs (74LVC4T3144 receiving buffer and
+74LVC1G07 OD driver) and the header for connecting to the FPGA board.  Note the
+absence of a SIM socket - hardware setups for sniffing a phone's communication
+with a real SIM on the one hand and for running with a software-emulated SIM on
+the other hand are different, and it does no good trying to combine them.
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/sim-fpc-pasv/pcb/Makefile	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,17 @@
+ALL=	gerbers.zip
+EXPARG=
+
+all:	${ALL}
+
+gerbers.d:	sim-fpc-pasv.pcb
+	-rm -rf $@
+	mkdir $@
+	pcb -x gerber --gerberfile gerbers.d/simfpc ${EXPARG} sim-fpc-pasv.pcb
+
+gerbers.zip:	gerbers.d
+	-rm -f $@
+	cd gerbers.d; zip ../gerbers.zip *
+
+clean:
+	rm -f *.ps *.pdf sim-fpc-pasv.pcb-
+	rm -rf gerbers.*
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/sim-fpc-pasv/pcb/sim-fpc-pasv.pcb	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,978 @@
+# release: pcb 20140316
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+	SymbolLine[10.00mil 50.00mil 20.00mil 50.00mil 8.00mil]
+	SymbolLine[5.00mil 45.00mil 10.00mil 50.00mil 8.00mil]
+)
+Symbol['q' 12.00mil]
+(
+	SymbolLine[20.00mil 35.00mil 20.00mil 65.00mil 8.00mil]
+	SymbolLine[15.00mil 30.00mil 20.00mil 35.00mil 8.00mil]
+	SymbolLine[5.00mil 30.00mil 15.00mil 30.00mil 8.00mil]
+	SymbolLine[0.0000 35.00mil 5.00mil 30.00mil 8.00mil]
+	SymbolLine[0.0000 35.00mil 0.0000 45.00mil 8.00mil]
+	SymbolLine[0.0000 45.00mil 5.00mil 50.00mil 8.00mil]
+	SymbolLine[5.00mil 50.00mil 15.00mil 50.00mil 8.00mil]
+	SymbolLine[15.00mil 50.00mil 20.00mil 45.00mil 8.00mil]
+)
+Symbol['r' 12.00mil]
+(
+	SymbolLine[5.00mil 35.00mil 5.00mil 50.00mil 8.00mil]
+	SymbolLine[5.00mil 35.00mil 10.00mil 30.00mil 8.00mil]
+	SymbolLine[10.00mil 30.00mil 20.00mil 30.00mil 8.00mil]
+	SymbolLine[0.0000 30.00mil 5.00mil 35.00mil 8.00mil]
+)
+Symbol['s' 12.00mil]
+(
+	SymbolLine[5.00mil 50.00mil 20.00mil 50.00mil 8.00mil]
+	SymbolLine[20.00mil 50.00mil 25.00mil 45.00mil 8.00mil]
+	SymbolLine[20.00mil 40.00mil 25.00mil 45.00mil 8.00mil]
+	SymbolLine[5.00mil 40.00mil 20.00mil 40.00mil 8.00mil]
+	SymbolLine[0.0000 35.00mil 5.00mil 40.00mil 8.00mil]
+	SymbolLine[0.0000 35.00mil 5.00mil 30.00mil 8.00mil]
+	SymbolLine[5.00mil 30.00mil 20.00mil 30.00mil 8.00mil]
+	SymbolLine[20.00mil 30.00mil 25.00mil 35.00mil 8.00mil]
+	SymbolLine[0.0000 45.00mil 5.00mil 50.00mil 8.00mil]
+)
+Symbol['t' 10.00mil]
+(
+	SymbolLine[5.00mil 10.00mil 5.00mil 45.00mil 8.00mil]
+	SymbolLine[5.00mil 45.00mil 10.00mil 50.00mil 8.00mil]
+	SymbolLine[0.0000 25.00mil 10.00mil 25.00mil 8.00mil]
+)
+Symbol['u' 12.00mil]
+(
+	SymbolLine[0.0000 30.00mil 0.0000 45.00mil 8.00mil]
+	SymbolLine[0.0000 45.00mil 5.00mil 50.00mil 8.00mil]
+	SymbolLine[5.00mil 50.00mil 15.00mil 50.00mil 8.00mil]
+	SymbolLine[15.00mil 50.00mil 20.00mil 45.00mil 8.00mil]
+	SymbolLine[20.00mil 30.00mil 20.00mil 45.00mil 8.00mil]
+)
+Symbol['v' 12.00mil]
+(
+	SymbolLine[0.0000 30.00mil 10.00mil 50.00mil 8.00mil]
+	SymbolLine[20.00mil 30.00mil 10.00mil 50.00mil 8.00mil]
+)
+Symbol['w' 12.00mil]
+(
+	SymbolLine[0.0000 30.00mil 0.0000 45.00mil 8.00mil]
+	SymbolLine[0.0000 45.00mil 5.00mil 50.00mil 8.00mil]
+	SymbolLine[5.00mil 50.00mil 10.00mil 50.00mil 8.00mil]
+	SymbolLine[10.00mil 50.00mil 15.00mil 45.00mil 8.00mil]
+	SymbolLine[15.00mil 30.00mil 15.00mil 45.00mil 8.00mil]
+	SymbolLine[15.00mil 45.00mil 20.00mil 50.00mil 8.00mil]
+	SymbolLine[20.00mil 50.00mil 25.00mil 50.00mil 8.00mil]
+	SymbolLine[25.00mil 50.00mil 30.00mil 45.00mil 8.00mil]
+	SymbolLine[30.00mil 30.00mil 30.00mil 45.00mil 8.00mil]
+)
+Symbol['x' 12.00mil]
+(
+	SymbolLine[0.0000 30.00mil 20.00mil 50.00mil 8.00mil]
+	SymbolLine[0.0000 50.00mil 20.00mil 30.00mil 8.00mil]
+)
+Symbol['y' 12.00mil]
+(
+	SymbolLine[0.0000 30.00mil 0.0000 45.00mil 8.00mil]
+	SymbolLine[0.0000 45.00mil 5.00mil 50.00mil 8.00mil]
+	SymbolLine[20.00mil 30.00mil 20.00mil 60.00mil 8.00mil]
+	SymbolLine[15.00mil 65.00mil 20.00mil 60.00mil 8.00mil]
+	SymbolLine[5.00mil 65.00mil 15.00mil 65.00mil 8.00mil]
+	SymbolLine[0.0000 60.00mil 5.00mil 65.00mil 8.00mil]
+	SymbolLine[5.00mil 50.00mil 15.00mil 50.00mil 8.00mil]
+	SymbolLine[15.00mil 50.00mil 20.00mil 45.00mil 8.00mil]
+)
+Symbol['z' 12.00mil]
+(
+	SymbolLine[0.0000 30.00mil 20.00mil 30.00mil 8.00mil]
+	SymbolLine[0.0000 50.00mil 20.00mil 30.00mil 8.00mil]
+	SymbolLine[0.0000 50.00mil 20.00mil 50.00mil 8.00mil]
+)
+Symbol['{' 12.00mil]
+(
+	SymbolLine[5.00mil 15.00mil 10.00mil 10.00mil 8.00mil]
+	SymbolLine[5.00mil 15.00mil 5.00mil 25.00mil 8.00mil]
+	SymbolLine[0.0000 30.00mil 5.00mil 25.00mil 8.00mil]
+	SymbolLine[0.0000 30.00mil 5.00mil 35.00mil 8.00mil]
+	SymbolLine[5.00mil 35.00mil 5.00mil 45.00mil 8.00mil]
+	SymbolLine[5.00mil 45.00mil 10.00mil 50.00mil 8.00mil]
+)
+Symbol['|' 12.00mil]
+(
+	SymbolLine[0.0000 10.00mil 0.0000 50.00mil 8.00mil]
+)
+Symbol['}' 12.00mil]
+(
+	SymbolLine[0.0000 10.00mil 5.00mil 15.00mil 8.00mil]
+	SymbolLine[5.00mil 15.00mil 5.00mil 25.00mil 8.00mil]
+	SymbolLine[5.00mil 25.00mil 10.00mil 30.00mil 8.00mil]
+	SymbolLine[5.00mil 35.00mil 10.00mil 30.00mil 8.00mil]
+	SymbolLine[5.00mil 35.00mil 5.00mil 45.00mil 8.00mil]
+	SymbolLine[0.0000 50.00mil 5.00mil 45.00mil 8.00mil]
+)
+Symbol['~' 12.00mil]
+(
+	SymbolLine[0.0000 35.00mil 5.00mil 30.00mil 8.00mil]
+	SymbolLine[5.00mil 30.00mil 10.00mil 30.00mil 8.00mil]
+	SymbolLine[10.00mil 30.00mil 15.00mil 35.00mil 8.00mil]
+	SymbolLine[15.00mil 35.00mil 20.00mil 35.00mil 8.00mil]
+	SymbolLine[20.00mil 35.00mil 25.00mil 30.00mil 8.00mil]
+)
+Attribute("PCB::grid::unit" "mil")
+Via[1150.00mil 500.00mil 60.00mil 20.00mil 0.0000 35.00mil "" "thermal(1X)"]
+Via[1270.00mil 290.00mil 60.00mil 20.00mil 0.0000 35.00mil "" "thermal(1X)"]
+Via[830.00mil 900.00mil 60.00mil 20.00mil 0.0000 35.00mil "" "thermal(1X)"]
+Via[1830.00mil 770.00mil 60.00mil 20.00mil 0.0000 35.00mil "" "thermal(1X)"]
+
+Element["" "WRFPC1_6_1L" "J1" "686106148922" 1370.00mil 150.00mil 160.00mil 10.00mil 0 100 ""]
+(
+	Pad[0.0000 5.9000mm 0.0000 6.6000mm 0.6000mm 0.1500mm 0.7500mm "" "1" "square,edge2"]
+	Pad[-1.0000mm 5.9000mm -1.0000mm 6.6000mm 0.6000mm 0.1500mm 0.7500mm "" "2" "square,edge2"]
+	Pad[-2.0000mm 5.9000mm -2.0000mm 6.6000mm 0.6000mm 0.1500mm 0.7500mm "" "3" "square,edge2"]
+	Pad[-3.0000mm 5.9000mm -3.0000mm 6.6000mm 0.6000mm 0.1500mm 0.7500mm "" "4" "square,edge2"]
+	Pad[-4.0000mm 5.9000mm -4.0000mm 6.6000mm 0.6000mm 0.1500mm 0.7500mm "" "5" "square,edge2"]
+	Pad[-5.0000mm 5.9000mm -5.0000mm 6.6000mm 0.6000mm 0.1500mm 0.7500mm "" "6" "square,edge2"]
+	Pad[2.2000mm 3.5000mm 2.4000mm 3.5000mm 1.8000mm 0.1500mm 1.9500mm "GND" "7" "square,edge2"]
+	Pad[-7.4000mm 3.5000mm -7.2000mm 3.5000mm 1.8000mm 0.1500mm 1.9500mm "GND" "8" "square"]
+	ElementLine [-337.77mil 282.65mil 140.92mil 282.65mil 10.00mil]
+	ElementLine [-337.77mil -11.00mil 140.92mil -11.00mil 10.00mil]
+	ElementLine [140.92mil -11.00mil 140.92mil 282.65mil 10.00mil]
+	ElementLine [-337.77mil -11.00mil -337.77mil 282.65mil 10.00mil]
+
+	)
+
+Element["" "" "J2" "CCM03-3009LFT" 1230.00mil 1050.00mil 460.00mil -420.00mil 0 100 ""]
+(
+	Pad[12.4000mm -150.00mil 12.4000mm -150.00mil 1.3000mm 0.1000mm 1.4500mm "C1" "1" "square,edge2"]
+	Pad[12.4000mm -50.00mil 12.4000mm -50.00mil 1.3000mm 0.1000mm 1.4500mm "C2" "2" "square,edge2"]
+	Pad[12.4000mm 50.00mil 12.4000mm 50.00mil 1.3000mm 0.1000mm 1.4500mm "C3" "3" "square,edge2"]
+	Pad[12.4000mm 150.00mil 12.4000mm 150.00mil 1.3000mm 0.1000mm 1.4500mm "SW1" "4" "square,edge2"]
+	Pad[-12.4000mm -150.00mil -12.4000mm -150.00mil 1.3000mm 0.1000mm 1.4500mm "C5" "5" "square"]
+	Pad[-12.4000mm -50.00mil -12.4000mm -50.00mil 1.3000mm 0.1000mm 1.4500mm "C6" "6" "square"]
+	Pad[-12.4000mm 50.00mil -12.4000mm 50.00mil 1.3000mm 0.1000mm 1.4500mm "C7" "7" "square"]
+	Pad[-12.4000mm 150.00mil -12.4000mm 150.00mil 1.3000mm 0.1000mm 1.4500mm "SW2" "8" "square"]
+	ElementLine [-16.8000mm -8.9000mm -16.8000mm 8.9000mm 0.1500mm]
+	ElementLine [-16.8000mm 8.9000mm 13.4500mm 8.9000mm 0.1500mm]
+	ElementLine [13.4500mm 8.9000mm 13.4500mm -8.9000mm 0.1500mm]
+	ElementLine [13.4500mm -8.9000mm -16.8000mm -8.9000mm 0.1500mm]
+
+	)
+
+Element["" "JUMPER4" "J3" "0901200924" 2070.00mil 800.00mil -30.00mil -130.00mil 0 100 ""]
+(
+	Pin[0.0000 0.0000 60.00mil 30.00mil 66.00mil 38.00mil "1" "1" "square,thermal(1X)"]
+	Pin[0.0000 100.00mil 60.00mil 30.00mil 66.00mil 38.00mil "2" "2" ""]
+	Pin[0.0000 200.00mil 60.00mil 30.00mil 66.00mil 38.00mil "3" "3" ""]
+	Pin[0.0000 300.00mil 60.00mil 30.00mil 66.00mil 38.00mil "4" "4" ""]
+	ElementLine [-50.00mil -50.00mil -50.00mil 350.00mil 20.00mil]
+	ElementLine [-50.00mil 350.00mil 50.00mil 350.00mil 20.00mil]
+	ElementLine [50.00mil 350.00mil 50.00mil -50.00mil 20.00mil]
+	ElementLine [50.00mil -50.00mil -50.00mil -50.00mil 20.00mil]
+	ElementLine [-50.00mil 50.00mil 50.00mil 50.00mil 10.00mil]
+	ElementLine [50.00mil 50.00mil 50.00mil -50.00mil 10.00mil]
+
+	)
+
+Element["" "JUMPER4" "J4" "0901200924" 260.00mil 800.00mil -30.00mil -130.00mil 0 100 ""]
+(
+	Pin[0.0000 0.0000 60.00mil 30.00mil 66.00mil 38.00mil "1" "1" "square,thermal(1X)"]
+	Pin[0.0000 100.00mil 60.00mil 30.00mil 66.00mil 38.00mil "2" "2" "thermal(1X)"]
+	Pin[0.0000 200.00mil 60.00mil 30.00mil 66.00mil 38.00mil "3" "3" ""]
+	Pin[0.0000 300.00mil 60.00mil 30.00mil 66.00mil 38.00mil "4" "4" ""]
+	ElementLine [-50.00mil -50.00mil -50.00mil 350.00mil 20.00mil]
+	ElementLine [-50.00mil 350.00mil 50.00mil 350.00mil 20.00mil]
+	ElementLine [50.00mil 350.00mil 50.00mil -50.00mil 20.00mil]
+	ElementLine [50.00mil -50.00mil -50.00mil -50.00mil 20.00mil]
+	ElementLine [-50.00mil 50.00mil 50.00mil 50.00mil 10.00mil]
+	ElementLine [50.00mil 50.00mil 50.00mil -50.00mil 10.00mil]
+
+	)
+
+Element["" "0603" "C1" "100n" 1830.00mil 870.00mil 44.09mil -51.50mil 0 100 ""]
+(
+	Pad[-4.92mil 25.59mil 4.92mil 25.59mil 29.52mil 20.00mil 35.52mil "1" "1" "square"]
+	Pad[-4.92mil -25.59mil 4.92mil -25.59mil 29.52mil 20.00mil 35.52mil "2" "2" "square"]
+	ElementLine [-28.59mil 48.27mil 28.59mil 48.27mil 6.00mil]
+	ElementLine [-28.59mil -48.27mil -28.59mil 48.27mil 6.00mil]
+	ElementLine [-28.59mil -48.27mil 28.59mil -48.27mil 6.00mil]
+	ElementLine [28.59mil -48.27mil 28.59mil 48.27mil 6.00mil]
+
+	)
+Layer(1 "component")
+(
+	Line[31.7980mm 10.0600mm 31.7980mm 25.8600mm 10.00mil 20.00mil "clearline"]
+	Line[31.7980mm 25.8600mm 1170.00mil 1100.00mil 10.00mil 20.00mil "clearline"]
+	Line[32.7980mm 10.0600mm 32.7980mm 25.6860mm 10.00mil 20.00mil "clearline"]
+	Line[32.7980mm 25.6860mm 1380.00mil 1100.00mil 10.00mil 20.00mil "clearline"]
+	Line[30.7980mm 10.0600mm 30.7980mm 22.2880mm 10.00mil 20.00mil "clearline"]
+	Line[30.7980mm 22.2880mm 1090.00mil 1000.00mil 10.00mil 20.00mil "clearline"]
+	Line[1090.00mil 1000.00mil 18.8420mm 1000.00mil 10.00mil 20.00mil "clearline"]
+	Line[33.7980mm 10.0600mm 33.7980mm 22.1140mm 10.00mil 20.00mil "clearline"]
+	Line[33.7980mm 22.1140mm 1460.00mil 1000.00mil 10.00mil 20.00mil "clearline"]
+	Line[1370.00mil 10.0600mm 1370.00mil 760.00mil 10.00mil 20.00mil "clearline"]
+	Line[1370.00mil 760.00mil 1510.00mil 900.00mil 10.00mil 20.00mil "clearline"]
+	Line[740.00mil 1000.00mil 260.00mil 1000.00mil 10.00mil 20.00mil "clearline"]
+	Line[1170.00mil 1100.00mil 260.00mil 1100.00mil 10.00mil 20.00mil "clearline"]
+	Line[1510.00mil 900.00mil 2070.00mil 900.00mil 10.00mil 20.00mil "clearline"]
+	Line[1460.00mil 1000.00mil 2070.00mil 1000.00mil 10.00mil 20.00mil "clearline"]
+	Line[1380.00mil 1100.00mil 2070.00mil 1100.00mil 10.00mil 20.00mil "clearline"]
+	Line[29.7980mm 10.0600mm 29.7980mm 12.1120mm 10.00mil 20.00mil "clearline"]
+	Line[29.7980mm 12.1120mm 1150.00mil 500.00mil 10.00mil 20.00mil "clearline"]
+	Line[18.8420mm 900.00mil 830.00mil 900.00mil 25.00mil 20.00mil "clearline"]
+	Line[1830.00mil 21.4480mm 1830.00mil 770.00mil 10.00mil 20.00mil "clearline"]
+	Line[27.4980mm 7.3100mm 37.0980mm 7.3100mm 40.00mil 20.00mil "clearline"]
+)
+Layer(2 "solder")
+(
+	Polygon("clearpoly")
+	(
+		[80.00mil 80.00mil] [2220.00mil 80.00mil] [2220.00mil 1520.00mil] [80.00mil 1520.00mil] 
+	)
+)
+Layer(3 "GND")
+(
+)
+Layer(4 "power")
+(
+)
+Layer(5 "signal1")
+(
+)
+Layer(6 "signal2")
+(
+)
+Layer(7 "signal3")
+(
+)
+Layer(8 "signal4")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+	Text[2140.00mil 770.00mil 0 100 "GND" "clearline"]
+	Text[2150.00mil 870.00mil 0 100 "VCC" "clearline"]
+	Text[2150.00mil 970.00mil 0 100 "RST" "clearline"]
+	Text[2150.00mil 1070.00mil 0 100 "CLK" "clearline"]
+	Text[90.00mil 770.00mil 0 100 "GND" "clearline"]
+	Text[90.00mil 870.00mil 0 100 "GND" "clearline"]
+	Text[90.00mil 970.00mil 0 100 "VPP" "clearline"]
+	Text[100.00mil 1070.00mil 0 100 "I/O" "clearline"]
+	Text[140.00mil 170.00mil 0 100 "SIMtrace FPC" "clearline"]
+	Text[140.00mil 240.00mil 0 100 "passive connection" "clearline"]
+	Text[140.00mil 410.00mil 0 100 "M. N. Falconia" "clearline"]
+)
+NetList()
+(
+	Net("CLK" "(unknown)")
+	(
+		Connect("J1-3")
+		Connect("J2-3")
+		Connect("J3-4")
+	)
+	Net("GND" "(unknown)")
+	(
+		Connect("C1-2")
+		Connect("J1-6")
+		Connect("J1-7")
+		Connect("J1-8")
+		Connect("J2-5")
+		Connect("J3-1")
+		Connect("J4-1")
+		Connect("J4-2")
+	)
+	Net("IO" "(unknown)")
+	(
+		Connect("J1-4")
+		Connect("J2-7")
+		Connect("J4-4")
+	)
+	Net("RST" "(unknown)")
+	(
+		Connect("J1-2")
+		Connect("J2-2")
+		Connect("J3-3")
+	)
+	Net("VCC" "(unknown)")
+	(
+		Connect("C1-1")
+		Connect("J1-1")
+		Connect("J2-1")
+		Connect("J3-2")
+	)
+	Net("VPP" "(unknown)")
+	(
+		Connect("J1-5")
+		Connect("J2-6")
+		Connect("J4-3")
+	)
+)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/sim-fpc-pasv/src/MCL	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,47 @@
+C1:
+ hier=C1
+ value=100n
+ footprint=0603
+ description=Ceramic chip capacitor, X7R, 0.1 uF, 0603
+ manufacturer=Samsung Electro-Mechanics
+ manufacturer_part_number=CL10B104KB8NNWC
+ vendor=Digi-Key
+ vendor_part_number=1276-1935-1-ND
+ npins=2
+
+J1:
+ hier=fpc
+ manufacturer=Wurth Elektronik
+ manufacturer_part_number=686106148922
+ description=FPC connector, 1 mm pitch, 6 pins, flip lock
+ vendor=Digi-Key
+ vendor_part_number=732-6017-1-ND
+ footprint=WRFPC1_6_1L	# pin 1 on the left
+ npins=8		# 6 actual pins + 2 mounting pads
+
+J2:
+ hier=sim
+ manufacturer=C&K Components
+ manufacturer_part_number=CCM03-3009LFT
+ description=SIM socket, full size, with latch
+ vendor=Digi-Key
+ vendor_part_number=401-1720-1-ND
+ footprint=file:SIM_Socket_TI
+ npins=8
+
+part header-4pin:
+ footprint=JUMPER4
+ description=Header, 0.100", single row, 4 posts
+ manufacturer=Molex
+ manufacturer_part_number=0901200924
+ vendor=Digi-Key
+ vendor_part_number=WM20580-ND
+ npins=4
+
+J3:
+ hier=tap_C1_C3
+ part=header-4pin
+
+J4:
+ hier=tap_C5_C7
+ part=header-4pin
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/sim-fpc-pasv/src/Makefile	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,28 @@
+BOMS=	tallied-bom.txt tallied-bom.csv comptab.txt
+NETS=	sverp.unet bound.unet pcb-netlist.txt
+
+all:	${BOMS} ${NETS} elements.pcb
+
+sverp.unet:	schem.v primitives
+	ueda-sverp -o $@ schem.v
+
+bound.unet:	MCL sverp.unet
+	unet-bind -c sverp.unet $@
+
+pcb-netlist.txt:	bound.unet
+	unet2pcb bound.unet $@
+
+tallied-bom.txt:	MCL
+	ueda-mkbom -cr > $@
+
+tallied-bom.csv:	MCL
+	ueda-csvbom > $@
+
+comptab.txt:	MCL
+	ueda-shortbom > $@
+
+elements.pcb:	MCL
+	ueda-getfps -ch | ueda-runm4 > $@
+
+clean:
+	rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/sim-fpc-pasv/src/primitives	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,5 @@
+capacitor	numpins 2;
+
+header_4pin	numpins 4;
+conn_6pin_plus2	numpins 8;
+pkg_SIM_socket	numpins 8;
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/boards/sim-fpc-pasv/src/schem.v	Mon Jul 17 00:52:00 2023 +0000
@@ -0,0 +1,40 @@
+module board ();
+
+wire GND, VCC, VPP, RST, CLK, IO;
+
+conn_6pin_plus2 fpc (.pin_1(VCC),
+		     .pin_2(RST),
+		     .pin_3(CLK),
+		     .pin_4(IO),
+		     .pin_5(VPP),
+		     .pin_6(GND),
+		     /* mounting pads */
+		     .pin_7(GND),
+		     .pin_8(GND)
+	);
+
+pkg_SIM_socket sim (.pin_1(VCC),
+		    .pin_2(RST),
+		    .pin_3(CLK),
+		    .pin_4(),		/* gap in footprint pin numbering */
+		    .pin_5(GND),
+		    .pin_6(VPP),
+		    .pin_7(IO),
+		    .pin_8()		/* gap in footprint pin numbering */
+	);
+
+capacitor C1 (VCC, GND);
+
+header_4pin tap_C1_C3 ( .pin_1(GND),
+			.pin_2(VCC),	/* C1 */
+			.pin_3(RST),	/* C2 */
+			.pin_4(CLK)	/* C3 */
+		);
+
+header_4pin tap_C5_C7 ( .pin_1(GND),
+			.pin_2(GND),	/* C5 */
+			.pin_3(VPP),	/* C6 */
+			.pin_4(IO)	/* C7 */
+		);
+
+endmodule