log

age author description
Mon, 21 Aug 2023 03:02:01 +0000 Mychaela Falconia boards/mv-sniffer: PCB layout done
Mon, 21 Aug 2023 01:12:16 +0000 Mychaela Falconia FPGA Makefile: generate timing.rpt
Mon, 21 Aug 2023 01:10:23 +0000 Mychaela Falconia FPGA Makefile: generate pnr.rpt
Mon, 21 Aug 2023 01:07:26 +0000 Mychaela Falconia fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
Mon, 21 Aug 2023 01:05:25 +0000 Mychaela Falconia fpga/sniffer-basic/sniff_rx.v: typo in signal name
Mon, 21 Aug 2023 01:00:16 +0000 Mychaela Falconia FPGA Makefile: capture yosys stdout
Mon, 21 Aug 2023 00:55:33 +0000 Mychaela Falconia FPGA Makefile: yosys-wrap installed on Mother's system
Mon, 21 Aug 2023 00:54:09 +0000 Mychaela Falconia .hgignore: add FPGA build products
Mon, 21 Aug 2023 00:52:00 +0000 Mychaela Falconia fpga/sniffer-basic: initial version
Sat, 29 Jul 2023 07:53:49 +0000 Mychaela Falconia doc: add ISO7816-specs pointer article
Sat, 29 Jul 2023 07:06:54 +0000 Mychaela Falconia doc: describe proposed FPGA design
Fri, 28 Jul 2023 21:10:48 +0000 Mychaela Falconia boards/mv-sniffer/src: generate elements.pcb
Fri, 28 Jul 2023 20:17:52 +0000 Mychaela Falconia boards/mv-sniffer/src: components bound to MCL
Fri, 28 Jul 2023 20:01:06 +0000 Mychaela Falconia beginning of mv-sniffer adapter board design
Mon, 17 Jul 2023 00:52:00 +0000 Mychaela Falconia starting project with README and sim-fpc-pasv adapter