FreeCalypso > hg > fc-sim-sniff
log
age | author | description |
---|---|---|
Mon, 21 Aug 2023 03:02:01 +0000 | Mychaela Falconia | boards/mv-sniffer: PCB layout done |
Mon, 21 Aug 2023 01:12:16 +0000 | Mychaela Falconia | FPGA Makefile: generate timing.rpt |
Mon, 21 Aug 2023 01:10:23 +0000 | Mychaela Falconia | FPGA Makefile: generate pnr.rpt |
Mon, 21 Aug 2023 01:07:26 +0000 | Mychaela Falconia | fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED |
Mon, 21 Aug 2023 01:05:25 +0000 | Mychaela Falconia | fpga/sniffer-basic/sniff_rx.v: typo in signal name |
Mon, 21 Aug 2023 01:00:16 +0000 | Mychaela Falconia | FPGA Makefile: capture yosys stdout |