| Mon, 21 Aug 2023 03:03:41 +0000 |
Mychaela Falconia |
boards/mv-sniffer/pcb: add Makefile
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| Mon, 21 Aug 2023 03:02:01 +0000 |
Mychaela Falconia |
boards/mv-sniffer: PCB layout done
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| Mon, 21 Aug 2023 01:12:16 +0000 |
Mychaela Falconia |
FPGA Makefile: generate timing.rpt
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| Mon, 21 Aug 2023 01:10:23 +0000 |
Mychaela Falconia |
FPGA Makefile: generate pnr.rpt
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| Mon, 21 Aug 2023 01:07:26 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
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| Mon, 21 Aug 2023 01:05:25 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/sniff_rx.v: typo in signal name
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| Mon, 21 Aug 2023 01:00:16 +0000 |
Mychaela Falconia |
FPGA Makefile: capture yosys stdout
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| Mon, 21 Aug 2023 00:55:33 +0000 |
Mychaela Falconia |
FPGA Makefile: yosys-wrap installed on Mother's system
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| Mon, 21 Aug 2023 00:54:09 +0000 |
Mychaela Falconia |
.hgignore: add FPGA build products
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| Mon, 21 Aug 2023 00:52:00 +0000 |
Mychaela Falconia |
fpga/sniffer-basic: initial version
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| Sat, 29 Jul 2023 07:53:49 +0000 |
Mychaela Falconia |
doc: add ISO7816-specs pointer article
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| Sat, 29 Jul 2023 07:06:54 +0000 |
Mychaela Falconia |
doc: describe proposed FPGA design
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| Fri, 28 Jul 2023 21:10:48 +0000 |
Mychaela Falconia |
boards/mv-sniffer/src: generate elements.pcb
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| Fri, 28 Jul 2023 20:17:52 +0000 |
Mychaela Falconia |
boards/mv-sniffer/src: components bound to MCL
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