| 19 months ago |
Mychaela Falconia |
doc/Sniffer-FPGA-design: update for finished work
|
| 19 months ago |
Mychaela Falconia |
doc/PPS-catcher-FSM: it has been implemented
|
| 19 months ago |
Mychaela Falconia |
sw/Makefile: add install
|
| 19 months ago |
Mychaela Falconia |
sw/sniff-rx/Makefile: add install
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-pps: add actual F/D control
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-*: forgot to change SIM_RST to SIM_RST_in for LED5
|
| 19 months ago |
Mychaela Falconia |
fpga: add top Makefile across projects
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-pps: first version
|
| 19 months ago |
Mychaela Falconia |
fpga tree: move icestick.pcf to common subdirectory
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-basic: drive pin 115 high for cardem pod
|
| 19 months ago |
Mychaela Falconia |
doc/Sniffer-FPGA-design: update for working status
|
| 19 months ago |
Mychaela Falconia |
doc/PPS-catcher-FSM: initial description
|
| 19 months ago |
Mychaela Falconia |
sw/Makefile: add
|
| 19 months ago |
Mychaela Falconia |
sw: simtrace3-sniff-rx program written, compiles
|
| 19 months ago |
Mychaela Falconia |
sw/libserial: based on FC host tools version
|
| 19 months ago |
Mychaela Falconia |
doc: on later thought, drop the DUS term in favor of ME/ID
|
| 19 months ago |
Mychaela Falconia |
FPGA make clean: rm *.rpt too
|
| 19 months ago |
Mychaela Falconia |
FPGA build: include yosys-wrap in this repository
|
| 19 months ago |
Mychaela Falconia |
doc/Sniffer-FPGA-design: update for first implementation
|
| 19 months ago |
Mychaela Falconia |
.hgignore: add mv-sniffer gerber files
|
| 19 months ago |
Mychaela Falconia |
boards/mv-sniffer/pcb: add Makefile
|
| 19 months ago |
Mychaela Falconia |
boards/mv-sniffer: PCB layout done
|
| 19 months ago |
Mychaela Falconia |
FPGA Makefile: generate timing.rpt
|
| 19 months ago |
Mychaela Falconia |
FPGA Makefile: generate pnr.rpt
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-basic/sniff_rx.v: typo in signal name
|
| 19 months ago |
Mychaela Falconia |
FPGA Makefile: capture yosys stdout
|
| 19 months ago |
Mychaela Falconia |
FPGA Makefile: yosys-wrap installed on Mother's system
|
| 19 months ago |
Mychaela Falconia |
.hgignore: add FPGA build products
|
| 19 months ago |
Mychaela Falconia |
fpga/sniffer-basic: initial version
|
| 20 months ago |
Mychaela Falconia |
doc: add ISO7816-specs pointer article
|
| 20 months ago |
Mychaela Falconia |
doc: describe proposed FPGA design
|
| 20 months ago |
Mychaela Falconia |
boards/mv-sniffer/src: generate elements.pcb
|
| 20 months ago |
Mychaela Falconia |
boards/mv-sniffer/src: components bound to MCL
|
| 20 months ago |
Mychaela Falconia |
beginning of mv-sniffer adapter board design
|
| 20 months ago |
Mychaela Falconia |
starting project with README and sim-fpc-pasv adapter
|
