| Mon, 21 Aug 2023 01:12:16 +0000 |
Mychaela Falconia |
FPGA Makefile: generate timing.rpt
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| Mon, 21 Aug 2023 01:10:23 +0000 |
Mychaela Falconia |
FPGA Makefile: generate pnr.rpt
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| Mon, 21 Aug 2023 01:07:26 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
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| Mon, 21 Aug 2023 01:05:25 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/sniff_rx.v: typo in signal name
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| Mon, 21 Aug 2023 01:00:16 +0000 |
Mychaela Falconia |
FPGA Makefile: capture yosys stdout
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| Mon, 21 Aug 2023 00:55:33 +0000 |
Mychaela Falconia |
FPGA Makefile: yosys-wrap installed on Mother's system
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| Mon, 21 Aug 2023 00:54:09 +0000 |
Mychaela Falconia |
.hgignore: add FPGA build products
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